AM79C30AVC datasheet(48/101 Pages) AMD

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Am79C30A/32A Data Sheet

Peripheral Port (PP)

Overview

The purpose of the Peripheral Port is to allow external

peripherals to be connected to the DSC/IDC circuit.

There are two basic modes of operation, Serial Bus

Port mode, and IOM-2 Terminal mode. Within IOM-2

Terminal mode, the DSC/IDC circuit may be configured

as any combination of IOM-2 timing/control master or

slave. The definition of the Peripheral Port pins de-

pends on the operating mode of the port, as described

in Table 50.

Serial Bus Port (SBP) Mode

The SBP mode of operation is backwards compatible

with the Revision D DSC circuit serial port and is en-

tered either following a device RESET or if pro-

grammed in PPCR1.

In SBP mode, the SCLK output provides a 192-kHz 1X

data clock of programmable polarity. The SBIN and

SBOUT pins support three 8-bit serial data channels,

designated Bd, Be, and Bf. The SFS output provides an

8-kHz serial frame sync pulse eight bit periods in width,

coincident with the Bd channel. The SBP mode timing

is illustrated in Figure 5.

Following a RESET, the SCLK and SFS outputs will de-

fault to a high-impedance state, which will be main-

tained until any MUX connection is programmed (or

until the Peripheral Port is programmed to an IOM-2

mode). SCLK and SFS will remain in a high-impedance

state if the Peripheral Port is explicitly disabled. The

SCLK and SFS signals are synchronized to the re-

ceived S-interface frame. If there is no S-interface

frame synchronization, the SCLK and SFS signals will

free-run at 192 kHz and 8 kHz respectively.

If the DSC/IDC circuit is programmed to Idle mode, the

SFS output is driven Low but SCLK continues to run. In

Power-Down mode, both the SFS and SCLK outputs

are high-impedance.

IOM-2 Terminal Mode Overview

The IOM-2 Interface standard encompasses both a Li-

necard mode and a Terminal mode. The Terminal

mode was defined to provide four functions, as follows:

1. Connection of multiple Layer-2 devices to a Layer-1

device (in this case, the Layer-1 device is the S/T In-

terface LIU). Provisi on for the connection of

non-IOM-2 devices is included.

2. Programming and control of Layer-1 or Layer-2 de-

vices that do not have a microprocessor interface,

for example, a U-interface transceiver.

Table 50.

Pin Operation versus Peripheral Port Modes

SBP

Port

Disabled

IOM-2 M

Activated

IOM-2 M

Deactivated

IOM-2 S*

Bus Reverse

Activated

IOM-2 S* Bus

Reverse

Deactivated

IOM-2 S No

Bus Reverse

Activated

IOM-2 S No

Bus Reverse

Deactivated

SBIN

IN/OD

SBOUT

OUT

OD/IN

SCLK

OUT

Low

SFS

OUT

Low

BCL/CH2STRB

OUT

Low

IN = Input

OUT = Output

Z = High Impedance

OD = Open Drain Output

Note:

*The Am79C30A is a non-Layer-1 component when operated in the Slave mode; however, it has a microprocessor interface.

As a result, it is required to change the direction of its I/O pins at certain times in order to communicate with both the upstream

Layer-1 device and any downstream peripheral devices. In the IOM-2 Slave mode, the direction of data flow is reversed with

respect to the DSC circuit during Sub-frame 0 and during the deactivated state. The rule is that the upstream Layer-1 device

only uses Sub-frame 0 and does not reverse its pins. Any non-Layer-1 component that does not contain a microprocessor

interface (i.e., program by the DSC circuit over the Monitor channel in Sub-frame 1) uses Sub-frame 0 to talk to the Layer-1

device and Sub-frame 1 to talk to the DSC circuit. It does not reverse its pins.

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