AM79C30AVC datasheet(46/101 Pages) AMD

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Am79C30A/32A Data Sheet

D-Channel Status Register 2 — (DSR2) — Read Only

DSR2 has the format illustrated in Table 46.

Note:

*Following RESET, the Transmit buffer Available (bit 4) is set, producing a default value of 10H.

The DSR2 bits generate interrupts and are set/reset under the conditions shown in Table 47 (in addition to a hard-

ware reset or Idle mode).

Table 46.

D-Channel Status Register 2

Bit

Logical 1

Logical 0 (Default Value)

Last byte of received packet

Not last byte of received packet

Receive byte available

Receive byte not available

Receive packet lost

Receive packet not lost

Last byte transmitted

Last byte not transmitted

Transmit buffer available

Transmit buffer not available*

Mark idle detected (15 or more contiguous 1s)

Mark idle not detected

Flag idle detected (more than two contiguous flags)

Flag idle not detected

Start of second received packet in FIFO

Second packet not yet in FIFO

Table 47.

DSR2 Interrupts

Bit

Generate Interrupt

Bit Set

Bit Reset

Yes, if DMR3 bit 2 = 1

When last byte of a received packet is read from the

DCRB

When the microprocessor reads the

DSR2

Yes, if DMR1 bit 3 = 1

When DCRB contains one or more bytes of data

When DCRB is empty

Yes, if DMR3 bit 6 = 1

When two outstanding packets are received and not

serviced, and a third packet is received

When the microprocessor reads

DSR2

Yes, if DMR3 bit 4 = 1

When the last byte of a transmit packet is transferred from

the DCTB

When the microprocessor reads

DSR2

Yes, if DMR3 bit 5 = 1

When the DCTB is available to be loaded with a data byte

When the DCTB is full

When 15 contiguous one bits have been detected in the

incoming D channel

When the first zero bit is detected

on the incoming D channel

When more than two contiguous flags are detected on the

incoming D channels, not including a closing flag

When a non-flag character is

detected on the incoming D channel

Yes, if EFCR bit 1 = 1

When start of second packet is in the receive FIFO

When second receive packet is not

present

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