AM79C30AVC datasheet(60/101 Pages) AMD

60 / 101 page

Am79C30A/32A Data Sheet

Peripheral Port Registers

The PP contains the following registers:

Peripheral Port Control Register 1 (PPCR1) Default = 01 Hex

Address = Indirect C0 Hex, Read/Write

Registers

# of Registers

Mnemonic

Peripheral Port Control Register

PPCR1, PPCR2, PPCR 3

Peripheral Port Status Register

PPSR

Peripheral Port Interrupt Enable Register

PPIER

Monitor Transmit Data Register

MTDR

Monitor Receive Data Register

MRDR

C/I Transmit Data Register

CITDR0, CITDR1

C/I Receive Data Register

CIRDR0, CIRDR1

654

MONTR

ABORT

RQST

MONTR

ENABL

MONTR

CHANL

SELECT

MONTR

EOM

RQST

CHANL

SELECT

IOM 2

ACTV/

DEACT

PORT

MODE

SELECT

BIT 1

PORT

MODE

SELECT

BIT0

Bit

Function

Monitor Channel Abort Request—This bit is automatically cleared during RESET or manually by software as follows:

to send an ABORT message, software should set this bit, wait at least two frames, then clear the bit.

Monitor Channel Enable—This bit only affects IOM-2 operation. When set, the selected monitor channel is enabled.

When cleared, both monitor channels are disabled. Whenever the monitor channel is disabled, the Monitor Transmit and

Receive Data Register (MTDR, MRDR) are updated to their default states: MTDR = FFH, MRDR = 00H.

Monitor Channel Select—This bit only affects IOM-2 operation. When set, Monitor channel 1 is used (second

subframe). When cleared, Monitor channel 0 is used (first subframe).

Monitor End-of-Message Request—When set, this bit forces the Monitor channel transmitter to send an EOM once all

data written into the Monitor Transmit Data Register has been transmitted. This tells the receiving device that the

message is complete. The bit is cleared by hardware when the EOM is sent by reset or by software.

IC Channel Select—This bit only affects IOM-2 operation. When set, the IC2 time slot is used (sixth octet after the frame

sync). When cleared, the IC1 time slot is used (fifth octet after the frame sync). The unused channel is always placed in

a high-impedance state.

IOM-2 Activation/Deactivation Bit—This bit only affects IOM-2 operation. Note that this bit controls only the starting

and stopping of SCLK, BCL/CH2STRB, SFS, and the state of the SBIN/SBOUT pins; this alone does not constitute

activation or deactivation of the IOM-2 bus. The activation/deactivation procedure involves the exchange of a series of

commands and indications over the C/I channel. This procedure, including a state diagram, is detailed in the IOM-2

specification.

IOM-2 Master mode—This bit is set by software. When deactivated, the master will turn on SCLK, BCL/CH2STRB, and

SFS clocks via software by setting this bit when the SBIN pin is pulled Low, indicating that a downstream device wishes

to communicate over the interface.

The IOM-2 activation/deactivation bit is cleared by software or reset. When cleared, the clocks are stopped, and SBIN is

monitored for the reactivation request from the slave (SBIN held Low). [Reset defaults the Peripheral Port to SBP

operation.]

IOM-2 Slave mode—This bit is set by software to initiate an activation request to the master. When set, the SBIN pin is

driven Low, and held Low until the activation/deactivation bit is cleared by software. In response to SBIN going Low the

master will start SCLK, which generates a timing request interrupt in the DSC circuit. The activation/deactivation bit is

cleared by software in response to this interrupt.

AM79C30AVC датащи(PDF) 60 Page - Advanced Micro Devices

AM79C30AVC датащи(HTML) 60 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL