AM79C30AVC datasheet(80/101 Pages) AMD

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Am79C30A/32A Data Sheet

Microprocessor Read/Write Timing

Microprocessor Read Timing

Microprocessor Write Timing

Notes:

1. The read/write recovery time of 200 ns holds in all cases except when a write command register operation is followed by a

read data register operation when accessing the MAP coefficient RAM. This operation requires a minimum recovery time of

450 ns.

2. Successive reads of the D-Channel Receive Buffer require a minimum cycle time (tRLRH + tRHRL) of 480 ns.

3. Read access time is measured from the falling edge of CS or the falling edge of RD, whichever occurs last.

4. CS may go Low before either RD or WR goes Low.

5. In minimal systems, CS may be tied Low.

6. Read and write indirect register operations cannot be mixed without at least one write command register operation between

them.

7. CS may go High before either RD or WR goes High.

8. If CS goes High before WR goes High, the minimum Address Hold time becomes 12 ns.

9. RD and WR pulse width, Address setup and hold, and Data setup and hold timing are measured from the points where both

CS and RD or WR are Low simultaneously.

Parameter Symbol

Parameter Description

Min

Max

Units

tRLRH

RD Pulse Width

200

tRHRL

Read Recovery Time (Notes 1, 2)

200

tAVRL

Address Valid to RD Low

tAHRH

Address Hold After RD High

tRHCH

RD High to CS High (Note 7)

tRACC

Read Access Time (Note 3)

tRHDZ

RD High to Data Hi-Z

tRDCS

RD Low to CS Low (Note 4)

Parameter Symbol

Parameter Description

Min

Max

Units

tWLWH

WR Pulse Width

200

tWHWL

Write Recovery Time (Note 1)

200

tAVWL

Address Valid to WR Low

tAHWH

Address Hold After WR High (Note 8)

tWHCH

WR High to CS High (Note 7)

tDSWH

Data Setup to WR High

100

tDHWH

Data Hold After WR High

tWRCS

WR Low to CS Low (Note 4)

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