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AM79C30AVC датащи(PDF) 44 Page - Advanced Micro Devices

номер детали AM79C30AVC
подробное описание детали  Digital Subscriber Controller??(DSC?? Circuit
PDF  101 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C30AVC датащи(HTML) 44 Page - Advanced Micro Devices

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Am79C30A/32A Data Sheet
D-Channel Mode Register 4 — (DMR4) — Read/Write
Address = Indirect 8FH
Note:
The receiver and transmitter thresholds can only be changed when the Am79C30A/32A is in Idle mode.
Address Status Register — (ASR) — Read Only
Address = Indirect 91H
Table 42.
D-Channel Mode Register 4
Bit
Control
Function
7
6
5
4
3
2
1
0
X
X
X
X
X
X
0
0
Receiver Threshold
1 byte (EFCR bit 0 = 0)
1 byte (EFCR bit 0 = 1)
X
X
X
X
X
X
0
1
2 bytes (EFCR bit 0 = 0)
16 bytes (EFCR bit 0 = 1)
X
X
X
X
X
X
1
0
4 bytes (EFCR bit 0 = 0)
24 bytes (EFCR bit 0 = 1)
X
X
X
X
X
X
1
1
8 bytes (EFCR bit 0 = 0)
30 bytes (EFCR bit 0 = 1)
X
X
X
X
0
0
X
X
Transmitter Threshold
1 byte (EFCR bit 0 = 0)
1 byte (EFCR bit 0 = 1)
X
X
X
X
0
1
X
X
2 bytes (EFCR bit 0 = 0)
6 bytes (EFCR bit 0 = 1)
X
X
X
X
1
0
X
X
4 bytes (EFCR bit 0 = 0)
10 bytes (EFCR bit 0 = 1)
X
X
X
X
1
1
X
X
8 bytes (EFCR bit 0 = 0)
14 bytes (EFCR bit 1 = 1)
X
X
X
0
X
X
X
X
Interframe Fill
Mark Idle (default value)
X
X
X
1
X
X
X
X
Flag Idle
X
X
0
X
X
X
X
X
Address Recognition
2-byte (default value)
0
X
1
X
X
X
X
X
First Received Byte only
1
X
1
X
X
X
X
X
Second Received Byte only
X
0
X
X
X
X
X
X
C/R Bit Compare
Disable FRAR bit 1 compare (default value)
X
1
X
X
X
X
X
X
Enable FRAR bit 1 compare
Table 43.
Address Status Register
Bit
Logical 1
Logical 0 (Default Value)
0
FRAR1/SRAR1 address recognized
No FRAR1/SRAR1 address match
1
FRAR2/SRAR2 address recognized
No FRAR2/SRAR2 address match
2
FRAR3/SRAR3 address recognized
No FRAR3/SRAR3 address match
3
FRAR4/SRAR4 address recognized
No FRAR4/SRAR4 address match
4–7
Reserved
Reserved



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