AM79C30AVC datasheet(62/101 Pages) AMD

62 / 101 page

Am79C30A/32A Data Sheet

Peripheral Port Interrupt Enable Register (PPIER) = 1

Default = Write = 00 Hex, Read = Bit 7 = 1, Bits 6–0 = 0

Address = Indirect C2 Hex, Read/Write

The Peripheral Port Interrupt Enable Register provides an individual interrupt-enable bit corresponding with eachof

the status conditions in the Peripheral Port Status Register. When set, the interrupt is enabled. Clearing the bit dis-

ables the interrupt. These bits are set and cleared by software.

Monitor Transmit Data Register (MTDR) Default = FF Hex

Address = Indirect C3 Hex, Write

The Monitor Transmit Data Register is the user-visible portion of the Monitor channel Transmitter Data buffer. Data

is written into this register by the user in response to a monitor transmit buffer available interrupt. It is then transmitted

to the receiver on the other side of the IOM-2 bus. The MTDR is emptied when the PP is reset.

Monitor Receive Data Register (MRDR) Default = 00 Hex

Address = Indirect C3 Hex, Read

The Monitor Receive Data Register is the user-visible portion of the Monitor channel Receiver Data buffer. Data is

written into this register by the hardware as it is received over the monitor channel. A monitor data available interrupt

is generated when the register is loaded. The register is overwritten by hardware only after the register has been

read. The default on reset is 00 hex.

654

PP/MF

INT EN

ENABL

IOM-2

TIME

RQST

ENABL

CHNG

IN C/I1

DATA

ENABL

CHNG

IN C/I0

DATA

ENABL

MONTR

ABORT

RECVD

ENABL

MONTR

EOM

RECVD

ENABL

MONTR

XMIT

BUFFR

AVAIL

ENABL

MONTR

RECV

DATA

AVAIL

Bit

Function

PP/MF Interrupt Enable—When set, this bit enables the Peripheral Port and Multiframing interrupts. When cleared, the

PP and MF interrupts are disabled.

Notes:

To ensure proper interrupt reporting, software must disable PP/MF interrupts when the interrupt routine is entered and

enable them when exiting.

654

DATA

BIT 7

(MSB)

DATA

BIT 6

DATA

BIT 5

DATA

BIT 4

DATA

BIT 3

DATA

BIT 2

DATA

BIT 1

DATA

BIT 0

(LSB)

654

DATA

BIT 7

(MSB)

DATA

BIT 6

DATA

BIT 5

DATA

BIT 4

DATA

BIT 3

DATA

BIT 2

DATA

BIT 1

DATA

BIT 0

(LSB)

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