AM79C30AVC datasheet(64/101 Pages) AMD

64 / 101 page

Am79C30A/32A Data Sheet

Peripheral Port Control Register 2 (PPCR2)

Default = Bits 7, 6, and 0 = 0, Bit 5 = 1, Bits 4–1 are Indeterminate*

Address = Indirect C8 Hex, Read/Write

The Peripheral Port Control Register 2 controls the inversion of the SCLK output in SBP mode. This provides flexi-

bility in the connection of peripheral devices to the DSC circuit. The hardware revision code is also contained in this

Note:

* The default value is revision-level dependent. Revision J will report a hardware revision code of 110.

Peripheral Port Control Register 3 (PPCR3)

Default = Bits 7–5 are Indeterminate, Bit 4=1, Bit 3=0, Bits 2-0= 1

Address = Indirect C9 Hex, Read/Write

654

REV

CODE

BIT 2

(MSB)

REV

CODE

BIT 1

REV

CODE

BIT 0

(LSB)

RSRVD

SCLK

INVRT

ENABL

Bit

Function

7–5

Hardware Revision Code—This read-only field reports the hardware revision level. Revision J of the DSC circuit will

report a hardware revision code of 110. The hardware revision codes for E and H are 100, 010, respectively.

SCLK Inversion Enable—When set, the SCLK output is inverted in SBP mode. When cleared, the SCLK output is

identical to the Revision D DSC circuit. This bit should not be changed while SCLK is enabled.

Bit

Function

7–5

RESERVED

SLAVE Mode Bus Reversal—PPCR3.4 controls the bus reversal function of the DSC’s IOM-2 SLAVE mode. By default

(PPCR3.4=1) the Slave bus reverses to ensure backwards compatibility with previous revisions. When PPCR3.4=0 the

IOM-2 bus will not reverse in SLAVE mode. This assures slave compatibility of the control function and allows use with

devices such as the ISAC-S.

TIC Bus Enable—PPCR3.3 controls enabling and disabling of TIC bus operation. When PPCR3.3=0 which is the default

condition, the IOM-2 bus will not support the TIC bus feature to ensure backwards compatibility with previous IOM-2

capable revisions of the 79C30A. The TIC bus control logic features are only enabled if PPCR3.3=1.

Features enabled when PPCR3.3=1

S/G bit

When the DSC is in IOM-2 MASTER mode the CTS output of the LIU is used to drive the transmitted S/G bit. This signal

indicates D-channel Clear To Send status and is set when the LIU collision detection logic fulfills the programmed priority

level requirements.

When in IOM-2 SLAVE mode the received S/G bit is used as the Clear To Send input into the DLC block.

TIC Address Bus and Bus Accessed

Refer to TIC bus operation section.

2–0

TIC Bus Address—Device address to be used on TIC bus. Default is 111.

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