AM79C30AVC datasheet(20/101 Pages) AMD

20 / 101 page

Am79C30A/32A Data Sheet

The three D-channel loopback controls defined in

LMR2 bits 0, 1, and 2 are explained below:

Bit 0, D-channel loopback at Am79C30A/32A enable:

This remote loopback is provided for maintenance pur-

poses from the NT’s perspective. The NT transmits

D-channel bits to the Am79C30A/32A where they are

internally looped (with the Data Link Controller) and

transmitted back to the NT. The incoming D-channel

data can be accessed by the microprocessor; however,

the microprocessor cannot send data on the outgoing

D channel.

Any difference between the transmitted D-channel bits

a nd t h e r e c e i ved E - c han ne l bi t s t o / f r om t h e

Am79C30A/32A (normally detected as an error which

halts the transmission) is ignored, thereby allowing the

transmission to continue.

Bit 1, D-channel loopback at LIU enable:

This local loopback is provided for local testing. Data on

the incoming D channel is ignored. The data from the

microprocessor is processed by the DLC and then

looped back to the microprocessor.

Bit 2, D-channel back-off disable:

This loopback is provided for maintenance purposes

from the TE’s perspective. The Am79C30A/32A trans-

mits D-channel bits to the NT where they are looped

and transmitted back to the Am79C30A/32A in the E

channel. The operation is normal except differences

between the D and E channels do not halt the trans-

mission.

Multiframe Register (MF), Read/Write

Address = Indirect A6H

Am79C30A

NT/PABX

Am79C30A

NT/PABX

MPI

Am79C30A

NT/PABX

Table 14.

Multiframe Register

Bit

Logical 1

Logical 0 (Default Value)

Enable Multiframe sync

Disable Multiframe sync

Enable S-data available interrupt

Disable interrupt

Enable Q-bit buffer empty interrupt

Disable interrupt

Enable Multiframe change of state interrupt

Disable interrupt

First subframe

Not first subframe

5, 6

Not used, reads logical 0

Multiframe synchronized (read only)

Multiframe not synchronized (read only)

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