A3P030 datasheet(125/220 Pages) MICROSEMI

125 / 220 page

ProASIC3 Flash Family FPGAs

Revision 13

3-3

should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,

simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be

considered.

Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both

Flash*Freeze mode and normal operation mode. No user intervention is required.

JTAG Pins

Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run

at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to

operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the

part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a

separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB

design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST

pin could be tied to GND.

TCK

Test Clock

Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-

up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor

placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.

Note that to operate at all VJTAG voltages, 500

 to 1 k will satisfy the requirements. Refer to Table 1

for more information.

TDI

Test Data Input

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor

on the TDI pin.

TDO

Test Data Output

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

TMS

Test Mode Select

The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an

internal weak pull-up resistor on the TMS pin.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active low input to asynchronously initialize (or reset) the boundary scan

circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-

down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor

values must be chosen from Table 1 and must satisfy the parallel resistance value requirement. The

values in Table 1 correspond to the resistor recommended when a single device is used, and the

equivalent parallel resistor when multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In

such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA

pin.

Note that to operate at all VJTAG voltages, 500

 to 1 k will satisfy the requirements.

Table 1 • Recommended Tie-Off Values for the TCK and TRST Pins

VJTAG

Tie-Off Resistance

VJTAG at 3.3 V

200

 to 1 k

VJTAG at 2.5 V

200

 to 1 k

VJTAG at 1.8 V

500

 to 1 k

VJTAG at 1.5 V

500

 to 1 k

Notes:

1. Equivalent parallel resistance if more than one device is on the JTAG chain

2. The TCK pin can be pulled up/down.

3. The TRST pin is pulled down.

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