A3P030 datasheet(98/220 Pages) MICROSEMI

номер детали	A3P030

подробное описание детали	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

PDF	220 Pages

Scroll/Zoom	100%

производитель	MICROSEMI [Microsemi Corporation]

домашняя страница	http://www.microsemi.com

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ProASIC3 DC and Switching Characteristics

2-84

Revision 13

Global Resource Characteristics

A3P250 Clock Tree Topology

Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The

global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250 device. It

is used to drive all D-flip-flops in the device.

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven

and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer

to the "Clock Conditioning Circuits" section on page 2-89. Table 2-108 to Table 2-114 on page 2-88

present minimum and maximum global clock delays within each device. Minimum and maximum delays

are measured with minimum and maximum loading.

Figure 2-27 • Example of Global Tree Use in an A3P250 Device for Clock Routing

Central

Global Rib

VersaTile

Rows

Global Spine

CCC

A3P030 датащи(PDF) 98 Page - Microsemi Corporation