A3P030 datasheet(124/220 Pages) MICROSEMI

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Pin Descriptions

3-2

Revision 13

insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can

be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals

will not be able to transition the device, even in bypass mode.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

VPUMP

Programming Supply Voltage

ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For

programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left

floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming

power supply voltage (VPUMP) range is listed in Table 2-2 on page 2-2.

When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in

parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

User Pins

I/O

User Input/Output

The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are

compatible with the I/O standard selected.

During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC

supplies continuously powered up, when the device transitions from programming to operating mode, the

I/Os are instantly configured to the desired user configuration.

Unused I/Os are configured as follows:

•

Output buffer is disabled (with tristate value of high impedance)

•

Input buffer is disabled (with tristate value of high impedance)

•

Weak pull-up is programmed

Globals

GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the

global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have

identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.

See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO

and ProASIC3 Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide. All inputs labeled GC/GF

are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2

are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into

the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global

network are multiplexed, and only one input can be used as a global input.

Refer to the I/O Structure section of the handbook for the device you are using for an explanation of the

naming of global pins.

Flash*Freeze Mode Activation Pin

Flash*Freeze is available on IGLOO, ProASIC3L, and RT ProASIC3 devices. It is not supported on

ProASIC3/E devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The

FF pin is active-low, has the same characteristics as a single-ended I/O, and must meet the maximum

rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a

regular I/O. For IGLOOe, ProASIC3EL, and RT ProASIC3 only, the FF pin can be configured as a

Schmitt trigger input.

When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering

Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted.

The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in

which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin

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