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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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A3P030 датащи(PDF) 93 Page - Microsemi Corporation |
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A3P030 датащи(HTML) 93 Page - Microsemi Corporation |
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93 / 220 page  ProASIC3 Flash Family FPGAs Revision 13 2-79 Timing Characteristics Figure 2-22 • Output DDR Timing Diagram 11 6 1 7 2 8 3 910 45 28 3 9 tDDROREMCLR tDDROHD1 tDDROREMCLR tDDROHD2 tDDROSUD2 tDDROCLKQ tDDRORECCLR CLK Data_R Data_F CLR Out tDDROCLR2Q 710 4 Table 2-104 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 ns tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 ns tDDROCKMPWH Clock Minimum Pulse Width High for the Output DDR 0.36 0.41 0.48 ns tDDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR 0.32 0.37 0.43 ns FDDOMAX Maximum Frequency for the Output DDR 350 309 263 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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