A3P030 datasheet(37/220 Pages) MICROSEMI

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ProASIC3 Flash Family FPGAs

Revision 13

2-23

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V,

Worst-Case VCCI (per standard)

Standard Plus I/O Banks

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA 12 mA High 35

– 0.45 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns

3.3 V LVCMOS

Wide Range2

100 µA 12 mA High 35

– 0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46 ns

2.5 V LVCMOS 12 mA 12 mA High 35

– 0.45 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns

1.8 V LVCMOS

8 mA 8 mA High 35

– 0.45 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns

1.5 V LVCMOS

4 mA 4 mA High 35

– 0.45 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns

3.3 V PCI

Per

PCI

spec

–

High 10 25 4 0.45 1.72 0.03 0.64 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

3.3 V PCI-X

Per

PCI-X

spec

–

High 10 25 4 0.45 1.72 0.03 0.62 0.32 1.76 1.27 2.08 2.41 3.42 2.94 ns

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-63 for

connectivity. This resistor is not required during normal operation.

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