A3P030 datasheet(28/220 Pages) MICROSEMI

28 / 220 page

ProASIC3 DC and Switching Characteristics

2-14

Revision 13

User I/O Characteristics

Timing Model

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case

VCC = 1.425 V

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL (Applicable to

Advanced I/O Banks Only)L

LVPECL

(Applicable

to Advanced

I/O Banks only)

LVDS,

BLVDS,

M-LVDS

(Applicable for

Advanced I/O

Banks only)

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

Combinational Cell

I/O Module

(Non-Registered)

LVTTLOutput drive strength = 8 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5 VOutput drive strength = 4 mA

High slew rate

LVTTLOutput drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL

Clock

Input LVTTL

Clock

Input LVTTL

Clock

tPD = 0.56 ns

tPD = 0.49 ns

tDP = 1.34 ns

tPD = 0.87 ns

tDP = 2.64 ns (Advanced I/O Banks)

tPD = 0.47 ns

tDP = 3.66 ns (Advanced I/O Banks)

tPD = 0.47 ns

tDP = 3.97 ns (Advanced I/O Banks)

tPD = 0.47 ns

tPY = 0.76 ns

(Advanced I/O Banks)

tCLKQ = 0.55 ns

tOCLKQ = 0.59 ns

tSUD = 0.43 ns

tOSUD = 0.31 ns

tDP = 2.64 ns

(Advanced I/O Banks)

tPY = 0.76 ns (Advanced I/O Banks)

tPY = 1.20 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

tPY = 0.76 ns

(Advanced I/O Banks)

tICLKQ = 0.24 ns

tISUD = 0.26 ns

tPY = 1.05 ns

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