JS28F256P30B95A datasheet(35/97 Pages) MICRON

35 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

9.0

Erase Operations

Flash erasing is performed on a block basis. An entire block is erased each time an

erase command sequence is issued, and only one block is erased at a time. When a

block is erased, all bits within that block read as logical ones. The following sections

describe block erase operations in detail.

9.1

Block Erase

Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to

be erased (see Section 6.0, “Command Set” on page 24). Next, the Block Erase Confirm command

is written to the address of the block to be erased. If the device is placed in standby (CE#

deasserted) during an erase operation, the device completes the erase operation before

entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 38, “Block

Erase Flowchart” on page 84).

During a block erase, the Write State Machine (WSM) executes a sequence of

internally-timed events that conditions, erases, and verifies all bits within the block.

Erasing the flash memory array changes “zeros” to “ones”. Memory array bits that are

ones can be changed to zeros only by programming the block (see Section 8.0,

“Program Operation” on page 29).

The Status Register can be examined for block erase progress and errors by reading

any address. The device remains in the Read Status Register state until another

command is written. SR[0] indicates whether the addressed block is erasing. Status

Status Register bit SR[7] indicates block erase status while the sequence executes.

When the erase operation has finished, Status Register bit SR[5] indicates an erase

failure if set. SR[3] set would indicate that the WSM could not perform the erase

operation because VPP was outside of its acceptable limits. SR[1] set indicates that the

erase operation attempted to erase a locked block, causing the operation to abort.

Before issuing a new command, the Status Register contents should be examined and

then cleared using the Clear Status Register command. Any valid command can follow

once the block erase operation has completed.

9.2

Erase Suspend

Issuing the Erase Suspend command while erasing suspends the block erase operation.

This allows data to be accessed from memory locations other than the one being

erased. The Erase Suspend command can be issued to any device address. A block

erase operation can be suspended to perform a word or buffer program operation, or a

read operation within any block except the block that is erase suspended (see

Figure 35, “Program Suspend/Resume Flowchart” on page 81).

When a block erase operation is executing, issuing the Erase Suspend command

requests the WSM to suspend the erase algorithm at predetermined points. The device

continues to output Status Register data after the Erase Suspend command is issued.

Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is

specified in Section 16.0, “Program and Erase Characteristics” on page 67.

To read data from the device (other than an erase-suspended block), the Read Array

command must be issued. During Erase Suspend, a Program command can be issued

to any block other than the erase-suspended block. Block erase cannot resume until

program operations initiated during erase suspend complete. Read Array, Read Status

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