JS28F256P30B95A datasheet(32/97 Pages) MICRON

32 / 97 page

P30

Datasheet

August 2008

306666-12

Note:

Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work

properly.

If the internal address counter increments beyond the block's maximum address, addressing wraps around to the

beginning of the block.

If the number of words is less than 32, remaining locations must be filled with 0xFFFF.

8.4.2

BEFP Setup Phase

After receiving the BEFP Setup and Confirm command sequence, Status Register bit

SR[7] (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup.

A delay before checking SR[7] is required to allow the WSM enough time to perform all

of its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected,

SR[4] is set and BEFP operation terminates. If the block was found to be locked, SR[1]

is also set. SR[3] is set if the error occurred due to an incorrect VPP level.

Note:

Reading from the device after the BEFP Setup and Confirm command sequence outputs

Status Register data. Do not issue the Read Status Register command; it will be interpreted

as data to be loaded into the buffer.

8.4.3

BEFP Program/Verify Phase

After the BEFP Setup Phase has completed, the host programming system must check

SR[7,0] to determine the availability of the write buffer for data streaming. SR[7]

cleared indicates the device is busy and the BEFP program/verify phase is activated.

SR[0] indicates the write buffer is available.

Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer

data programming to the array. For BEFP, the count value for buffer loading is always

the maximum buffer size of 32 words. During the buffer-loading sequence, data is

stored to sequential buffer locations starting at address 0x00. Programming of the

buffer contents to the flash memory array starts as soon as the buffer is full. If the

number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF.

Caution:

The buffer must be completely filled for programming to occur. Supplying an

address outside of the current block's range during a buffer-fill sequence

causes the algorithm to exit immediately. Any data previously loaded into the

buffer during the fill cycle is not programmed into the array.

The starting address for data entry must be buffer size aligned, if not the BEFP

algorithm will be aborted and the program fails and (SR[4]) flag will be set.

Data words from the write buffer are directed to sequential memory locations in the

flash memory array; programming continues from where the previous buffer sequence

ended. The host programming system must poll SR[0] to determine when the buffer

program sequence completes. SR[0] cleared indicates that all buffer data has been

transferred to the flash array; SR[0] set indicates that the buffer is not available yet for

the next fill cycle. The host system may check full status for errors at any time, but it is

Table 16: BEFP Considerations

Parameter/Issue

Requirement

Notes

Cycling

For optimum performance, cycling must be limited below 100 erase cycles per block.

Programming blocks

BEFP programs one block at a time; all buffer data must fall within a single block

Suspend

BEFP cannot be suspended

Programming the flash

memory array

Programming to the flash memory array can occur only when the buffer is full.

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