JS28F256P30B95A datasheet(45/97 Pages) MICRON

45 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

11.2.4

Data Hold

For burst read operations, the Data Hold (DH) bit determines whether the data output

remains valid on DQ[15:0] for one or two clock cycles. This period of time is called the

“data cycle”. When DH is set, output data is held for two clocks (default). When DH is

cleared, output data is held for one clock (see Figure 15). The processor’s data setup

time and the flash memory’s clock-to-data output delay should be considered when

determining whether to hold output data for one or two clocks. A method for

determining the Data Hold configuration is shown below:

To set the device at one clock data hold for subsequent reads, the following condition

must be satisfied:

tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)

tDATA = Data set up to Clock (defined by CPU)

For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming

tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:

20 ns + 4 ns ≤ 25 ns

The equation is satisfied and data will be available at every clock period with data hold

setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of

2 clock periods must be used.

11.2.5

WAIT Delay

The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during

synchronous burst reads. WAIT can be asserted either during or one data cycle before

valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle

before valid data (default). When WD is cleared, WAIT is deasserted during valid data.

All Asynchronous Reads

Deasserted

All Writes

High-Z

1,2

Notes:

Active: WAIT is asserted until data becomes valid, then deasserts

When OE# = VIH during writes, WAIT = High-Z

Table 21: WAIT Functionality Table (Sheet 2 of 2)

Condition

WAIT

Notes

Figure 15: Data Hold Timing

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

CLK [C]

D[15:0] [Q]

2 CLK

Data Hold

1 CLK

Data Hold

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