JS28F256P30B95A datasheet(23/97 Pages) MICRON

23 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

5.4

Standby

When CE# is deasserted the device is deselected and placed in standby, substantially

reducing power consumption. In standby, the data outputs are placed in High-Z,

independent of the level placed on OE#. Standby current, ICCS, is the average current

measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,

average current is measured over the same time interval 5 μs after CE# is deasserted.

When the device is deselected (while CE# is deasserted) during a program or erase

operation, it continues to consume active power until the program or erase operation is

completed.

5.5

Reset

As with any automated device, it is important to assert RST# when the system is reset.

When the system comes out of reset, the system processor attempts to read from the

flash memory if it is the system boot device. If a CPU reset occurs with no flash

memory reset, improper CPU initialization may occur because the flash memory may

be providing status information rather than array data. Flash memory devices from

Numonyx allow proper CPU initialization following a system reset through the use of the

RST# input. RST# should be controlled by the same low-true reset signal that resets

the system CPU.

After initial power-up or reset, the device defaults to asynchronous Read Array mode,

and the Status Register is set to 0x80. Asserting RST# de-energizes all internal

circuits, and places the output drivers in High-Z. When RST# is asserted, the device

shuts down the operation in progress, a process which takes a minimum amount of

time to complete. When RST# has been deasserted, the device is reset to

asynchronous Read Array state.

Note:

If RST# is asserted during a program or erase operation, the operation is terminated and the

memory contents at the aborted location (for a program) or block (for an erase) are no longer

valid, because the data may have been only partially written or erased.

When returning from a reset (RST# deasserted), a minimum wait is required before the

initial read access outputs valid data. Also, a minimum delay is required after a reset

before a write cycle can be initiated. After this wake-up interval passes, normal

operation is restored. See Section 15.0, “AC Characteristics” on page 55 for details

about signal-timing.

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