JS28F256P30B95A datasheet(31/97 Pages) MICRON

31 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

If an attempt is made to program past an erase-block boundary using the Buffered

Program command, the device aborts the operation. This generates a command

sequence error, and Status Register bits SR[5,4] are set.

If Buffered programming is attempted while VPP is below VPPLK, Status Register bits

SR[4,3] are set. If any errors are detected that have set Status Register bits, the

Status Register should be cleared using the Clear Status Register command.

8.4

Buffered Enhanced Factory Programming

Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash

programming. The enhanced programming algorithm used in BEFP eliminates

traditional programming elements that drive up overhead in device programmer

systems.

BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 37, “BEFP

Flowchart” on page 83). It uses a write buffer to spread MLC program performance

across 32 data words. Verification occurs in the same phase as programming to

accurately program the flash memory cell to the correct bit state.

A single two-cycle command sequence programs the entire block of data. This

enhancement eliminates three write cycles per buffer: two commands and the word

count for each set of 32 data words. Host programmer bus cycles fill the device’s write

buffer followed by a status check. SR[0] indicates when data from the buffer has been

programmed into sequential flash memory array locations.

Following the buffer-to-flash array programming sequence, the Write State Machine

(WSM) increments internal addressing to automatically select the next 32-word array

boundary. This aspect of BEFP saves host programming equipment the address-bus

setup overhead.

With adequate continuity testing, programming equipment can rely on the WSM’s

internal verification to ensure that the device has programmed properly. This eliminates

the external post-program verification and its associated overhead.

8.4.1

BEFP Requirements and Considerations

Note:

Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] =

0x00.

Table 15: BEFP Requirements

Parameter/Issue

Requirement

Notes

Case Temperature

TC = 25 °C ± 5 °C

VCC

Within operating range

VPP

Driven to VPPH

Setup and Confirm

Target block unlocked before issuing the BEFP Setup and Confirm commands

Programming

The first-word address (WA0) of the block to be programmed must be held constant

from the setup phase through all data streaming into the target block, until transition

to the exit phase is desired

Buffer Alignment

WA0 must align with the start of an array buffer boundary

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