JS28F256P30B95A datasheet(5/97 Pages) MICRON

5 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

1.0

Functional Description

1.1

Introduction

This document provides information about the Numonyx™ StrataFlash® Embedded

Memory (P30) product and describes its features, operation, and specifications.

The Numonyx™ StrataFlash® Embedded Memory (P30) product is the latest generation

of Numonyx™ StrataFlash® memory devices. Offered in 64-Mbit up through 512-Mbit

densities, the P30 device brings reliable, two-bit-per-cell storage technology to the

embedded flash market segment. Benefits include more density in less space, high-

speed interface, lowest cost-per-bit NOR device, and support for code and data

storage. Features include high-performance synchronous-burst read mode, fast

asynchronous access times, low power, flexible security options, and three industry

standard package choices. The P30 product family is manufactured using Intel* 130 nm

ETOX™ VIII process technology.

The P30 product family is also planned on the Intel* 65nm process lithography. 65nm

AC timing changes are noted in this datasheet, and should be taken into account for all

new designs.

1.2

Overview

This section provides an overview of the features and capabilities of the P30.

The P30 family provides density upgrades from 64-Mbit through 512-Mbit. This family

of devices provides high performance at low voltage on a 16-bit data bus. Individually

erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-

mode read. Configuring the Read Configuration Register enables synchronous burst-

mode reads. In synchronous burst mode, output data is synchronized with a user-

supplied clock signal. A WAIT signal provides an easy CPU-to-flash memory

synchronization.

In addition to the enhanced architecture and interface, the device incorporates

technology that enables fast factory program and erase operations. Designed for low-

voltage systems, the

P30 supports read operations with VCC at 1.8 V, and erase and program operations with

VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the

fastest flash array programming performance with VPP at 9.0 V, which increases factory

throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low

power design. In addition to voltage flexibility, a dedicated VPP connection provides

complete data protection when VPP ≤ VPPLK.

A Command User Interface (CUI) is the interface between the system processor and all

internal operations of the device. An internal Write State Machine (WSM) automatically

executes the algorithms and timings necessary for block erase and program. A Status

An industry-standard command sequence invokes program and erase automation. Each

erase operation erases one block. The Erase Suspend feature allows system software to

pause an erase cycle to read or program data in another block. Program Suspend

allows system software to pause programming to read other locations. Data is

programmed in word increments (16 bits).

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