JS28F256P30B95A datasheet(69/97 Pages) MICRON

69 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

17.2

SCSP Products

Note:

For 512-Mbit only, “B” is used for both top and bottom Parameter/Mux configurations.

Note:

* The “B” parameter is used for both “top” and “bottom” options in the 512-Mbit density.

Figure 33: Decoder for SCSP P30

Table 36: Valid Combinations for Dual- Die Products

64-Mbit

128-Mbit

256-Mbit

512-Mbit*

RD48F2000P0ZBQ0

RD48F3000P0ZBQ0

RD48F4000P0ZBQ0

RD48F4400P0VBQ0

RD48F2000P0ZTQ0

RD48F3000P0ZTQ0

RD48F4000P0ZTQ0

PF48F4400P0VBQ0

PF48F2000P0ZBQ0

PF48F3000P0ZBQ0

PF48F4000P0ZBQ0

RC48F4400P0VB00

PF48F2000P0ZTQ0

PF48F3000P0ZTQ0

PF48F4000P0ZTQ0

PC48F4400P0VB00

TE48F4400P0VB00

JS48F4400P0VB00

F 4 0

P 0 Z B

D 4

0 0

G roup De signator

48F = Flash Memory only

P ackag e D esign ator

RD = Intel® SCSP, leaded

P F = Intel® SCSP, lead-free

RC = 64-Ball Easy BGA, leaded

P C = 64-Ball Easy BGA, lead-free

TE = 56-Lead TSOP , leaded

JS = 56-Lead TSOP, lead-free

Flash Density

0 = No die

2 = 64-Mbit

3 = 128-M bit

4 = 256-M bit

P ro duc t Fam ily

P = Intel StrataFlash® Em bedded M em ory

0 = No die

De vice D etails

0 = Original version of the product

(refer to the latest version of the

datasheet for details)

Ba llout Designator

Q = QUAD+ ballout

0 = Discrete ballout

Param ete r, M u x C onfig uration

B = Bottom Param eter, Non Mux

T = Top Param eter, Non M ux

I/O V oltag e, C E# C on figu ratio n

Z = Individual Chip Enable(s)

V = Virtual Chip E nable(s)

VCC = 1.7 V – 2.0 V

VCCQ = 1.7 V – 3.6 V

JS28F256P30B95A датащи(PDF) 69 Page - Micron Technology

JS28F256P30B95A датащи(HTML) 69 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

датащи скачать

ссылки URL