M68ICS08GR datasheet(134/408 Pages) FREESCALE

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Computer Operating Properly (COP)

Technical Data

MC68HC908GR8 — Rev 4.0

134

Computer Operating Properly (COP)

MOTOROLA

Figure 9-1. COP Block Diagram

The COP counter is a free-running 6-bit counter preceded by a 12-bit

prescaler counter. If not cleared by software, the COP counter overflows

and generates an asynchronous reset after 218 – 24 or 213 – 24

CGMXCLK cycles, depending on the state of the COP rate select bit,

COPRS, in the configuration register. With a 213 – 24 CGMXCLK cycle

overflow option, a 32.768-kHz crystal gives a COP timeout period of

250 ms. Writing any value to location $FFFF before an overflow occurs

prevents a COP reset by clearing the COP counter and stages 12

through 5 of the prescaler.

NOTE:

Service the COP immediately after reset and before entering or after

exiting stop mode to guarantee the maximum time before the first COP

counter overflow.

A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the

COP bit in the reset status register (RSR).

COPCTL WRITE

CGMXCLK

RESET VECTOR FETCH

RESET CIRCUIT

RESET STATUS REGISTER

INTERNAL RESET SOURCES

12-BIT COP PRESCALER

6-BIT COP COUNTER

COP DISABLE

RESET

COPCTL WRITE

CLEAR

COP MODULE

COPEN (FROM SIM)

COP COUNTER

COP CLOCK

STOP INSTRUCTION

(FROM CONFIG)

COP RATE SEL

(FROM CONFIG)

Freescale Semiconductor, Inc.

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