M68ICS08GR datasheet(131/408 Pages) FREESCALE

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Configuration Register (CONFIG)

Functional Description

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Configuration Register (CONFIG)

131

OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit

OSCSTOPENB enables the oscillator to continue operating during stop

mode. Setting the OSCSTOPENB bit allows the oscillator to operate

continuously even during stop mode. This is useful for driving the

timebase module to allow it to generate periodic wakeup while in stop

mode. (See Clock Generator Module (CGM) subsection Stop Mode.)

1 = Oscillator enabled to operate during stop mode

0 = Oscillator disabled during stop mode (default)

SCIBDSRC — SCI Baud Rate Clock Source Bit

SCIBDSRC controls the clock source used for the SCI. The setting of

this bit affects the frequency at which the SCI operates.

1 = Internal data bus clock used as clock source for SCI

0 = External oscillator used as clock source for SCI

COPRS — COP Rate Select Bit

COPRS selects the COP timeout period. Reset clears COPRS. See

Computer Operating Properly (COP).

1 = COP timeout period = 213 – 24 CGMXCLK cycles

0 = COP timeout period = 218 – 24 CGMXCLK cycles

LVISTOP — LVI Enable in Stop Mode Bit

When the LVIPWRD bit is clear, setting the LVISTOP bit enables the

LVI to operate during stop mode. Reset clears LVISTOP. See Stop

Mode.

1 = LVI enabled during stop mode

0 = LVI disabled during stop mode

LVIRSTD — LVI Reset Disable Bit

LVIRSTD disables the reset signal from the LVI module. See Low-

Voltage Inhibit (LVI).

1 = LVI module resets disabled

0 = LVI module resets enabled

LVIPWRD — LVI Power Disable Bit

LVIPWRD disables the LVI module. See Low-Voltage Inhibit (LVI).

1 = LVI module power disabled

0 = LVI module power enabled

Freescale Semiconductor, Inc.

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