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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M68ICS08GR датащи(PDF) 136 Page - Freescale Semiconductor, Inc |
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M68ICS08GR датащи(HTML) 136 Page - Freescale Semiconductor, Inc |
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136 / 408 page  Computer Operating Properly (COP) Technical Data MC68HC908GR8 — Rev 4.0 136 Computer Operating Properly (COP) MOTOROLA 9.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 9.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Configuration Register (CONFIG). 9.4.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See Configuration Register (CONFIG). 9.5 COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector. 9.6 Interrupts The COP does not generate CPU interrupt requests. Address: $FFFF Bit 7 6 54321 Bit 0 Read: Low byte of reset vector Write: Clear COP counter Reset: Unaffected by reset Figure 9-2. COP Control Register (COPCTL) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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