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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OR2C04A датащи(PDF) 92 Page - List of Unclassifed Manufacturers |
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OR2C04A датащи(HTML) 92 Page - List of Unclassifed Manufacturers |
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92 / 192 page  Data Sheet ORCA Series 2 FPGAs June 1999 92 Lucent Technologies Inc. Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout Pin 2C/2T06A Pad 2C/2T08A Pad 2C/2T10A Pad 2C/2T12A Pad 2C/2T15A/B Pad Function C2 PL1D PL1D PL1D PL1D PL1D I/O D2 PL1C PL1B PL1B PL1C PL1C I/O D3 PL1B PL1A PL1A PL1B PL1B I/O E4 PL1A PL2D PL2D PL2D PL2D I/O-A0 C1 — PL2C PL2C PL2C PL2A I/O D1 — PL2B PL2B PL2B PL3D I/O E3 — PL2A PL2A PL2A PL3A I/O E2 PL2D PL3D PL3D PL3D PL4D I/O-VDD5 E1 PL2C PL3C PL3C PL3A PL4A I/O F3 PL2B PL3B PL3B PL4D PL5D I/O G4 PL2A PL3A PL3A PL4A PL5A I/O-A1 F2 — — PL4D PL5D PL6D I/O F1 PL3D PL4D PL4A PL5A PL6A I/O-A2 G3 PL3C PL4C PL5C PL6D PL7D I/O G2 PL3B PL4B PL5B PL6B PL7B I/O G1 PL3A PL4A PL5A PL6A PL7A I/O-A3 H3 PL4D PL5D PL6D PL7D PL8D I/O H2 PL4C PL5C PL6C PL7C PL8C I/O H1 PL4B PL5B PL6B PL7B PL8B I/O J4 PL4A PL5A PL6A PL7A PL8A I/O-A4 J3 PL5D PL6D PL7D PL8D PL9D I/O-A5 J2 PL5C PL6C PL7C PL8C PL9C I/O J1 PL5B PL6B PL7B PL8B PL9B I/O K2 PL5A PL6A PL7A PL8A PL9A I/O-A6 K3 PL6D PL7D PL8D PL9D PL10D I/O K1 PL6C PL7C PL8C PL9C PL10C I/O L1 PL6B PL7B PL8B PL9B PL10B I/O L2 PL6A PL7A PL8A PL9A PL10A I/O-A7 L3 PL7D PL8D PL9D PL10D PL11D I/O L4 PL7C PL8C PL9C PL10C PL11C I/O-VDD5 M1 PL7B PL8B PL9B PL10B PL11B I/O M2 PL7A PL8A PL9A PL10A PL11A I/O-A8 M3 PL8D PL9D PL10D PL11D PL12D I/O-A9 M4 PL8C PL9C PL10C PL11C PL12C I/O N1 PL8B PL9B PL10B PL11B PL12B I/O N2 PL8A PL9A PL10A PL11A PL12A I/O-A10 N3 PL9D PL10D PL11D PL12D PL13D I/O P1 PL9C PL10C PL11C PL12C PL13C I/O P2 PL9B PL10B PL11B PL12B PL13B I/O R1 PL9A PL10A PL11A PL12A PL13A I/O-A11 Notes: The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table. The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17. The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series. The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected. |
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