OR2C04A datasheet(46/192 Pages) ETC

46 / 192 page

Data Sheet

ORCA Series 2 FPGAs

June 1999

Lucent Technologies Inc.

Configuration Data Format (continued)

Table 9. Configuration Frame Format and Contents

Note:

For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must

be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive

integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit

stream generator tool supplies a bit stream which is compatible with all configuration modes, including slave parallel mode.

Header

11111111

Leading header—4 bits minimum dummy bits

0010

Preamble

24-Bit Length Count

Configuration frame length

1111

Trailing header—4 bits minimum dummy bits

ID Frame

(Optional)

Frame start

P—1

Must be set to 1 to indicate data frame

C—0

Must be set to 0 to indicate uncompressed

Opar, Epar

Frame parity bits

Addr[10:0] =

11111111111

ID frame address

Prty_En

Set to 1 to enable parity

Reserved [42:0]

Reserved bits set to 0

20-bit part ID

111

Three or more stop bits (high) to separate frames

Configuration

Data

Frame

(repeated for

each data frame)

Frame start

P—1 or 0

1 indicates data frame; 0 indicates all frames are written

C—1 or 0

Uncompressed—0 indicates data and address are supplied;

Compressed—1 indicates only address is supplied

Opar, Epar

Frame parity bits

Addr[10:0]

Column address in FPGA to be written

Alignment bit (different number of 0s needed for each part)

Write bit—used in uncompressed data frame

Data Bits

Needed only in an uncompressed data frame

111

One or more stop bits (high) to separate frames

End of

Configuration

0010011111111111

16 bits—00 indicates all frames are written

Postamble

111111 . . . . .

Additional 1s

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