OR2C04A datasheet(42/192 Pages) ETC

42 / 192 page

Lucent Technologies Inc.

Data Sheet

ORCA Series 2 FPGAs

June 1999

FPGA States of Operation (continued)

Start-Up

After configuration, the FPGA enters the start-up

phase. This phase is the transition between the config-

uration and operational states and begins when the

number of CCLKs received after INIT goes high is equal

to the value of the length count field in the configuration

frame and when the end of configuration frame has

been written. The system design issue in the start-up

phase is to ensure the user I/Os become active without

inadvertently activating devices in the system or caus-

ing bus contention. A second system design concern is

the timing of the release of global set/reset of the PLC

latches/FFs.

There are configuration options that control the relative

timing of three events: DONE going high, release of the

set/reset of internal FFs, and user I/Os becoming

active. Figure 38 shows the start-up timing for both the

ORCA and ATT3000 Series FPGAs. The system

designer determines the relative timing of the I/Os

becoming active, DONE going high, and the release of

the set/reset of internal FFs. In the

ORCA Series

FPGA, the three events can occur in any arbitrary

sequence. This means that they can occur before or

after each other, or they can occur simultaneously.

There are four main start-up modes: CCLK_NOSYNC,

CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC.

The only difference between the modes starting with

CCLK and those starting with UCLK is that for the

UCLK modes, a user clock must be supplied to the

start-up logic. The timing of start-up events is then

based upon this user clock, rather than CCLK. The dif-

ference between the SYNC and NOSYNC modes is

that, for SYNC mode, the timing of two of the start-up

events (release of the set/reset of internal FFs and the

I/Os becoming active) is triggered by the rise of the

external DONE pin followed by a variable number of ris-

ing clock edges (either CCLK or UCLK). For the

NOSYNC mode, the timing of these two events is

based only on either CCLK or UCLK.

DONE is an open-drain bidirectional pin that may

include an optional (enabled by default) pull-up resistor

to accommodate wired ANDing. The open-drain DONE

signals from multiple FPGAs can be tied together

(ANDed) with a pull-up (internal or external) and used

as an active-high ready signal, an active-low PROM

enable, or a reset to other portions of the system.

When used in SYNC mode, these ANDed DONE pins

can be used to synchronize the other two start-up

events, since they can all be synchronized to the same

external signal. This signal will not rise until all FPGAs

release their DONE pins, allowing the signal to be

pulled high.

The default for

ORCA is the CCLK_SYNC synchro-

nized start-up mode where DONE is released on the

first CCLK rising edge, C1 (see Figure 38). Since this is

a synchronized start-up mode, the open-drain DONE

signal can be held low externally to stop the occurrence

of the other two start-up events. Once the DONE pin

has been released and pulled up to a high level, the

other two start-up events can be programmed individu-

ally to either happen immediately or after up to four ris-

ing edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4).

The default is for both events to happen immediately

after DONE is released and pulled high.

A commonly used design technique is to release

DONE one or more clock cycles before allowing the I/O

to become active. This allows other configuration

devices, such as PROMs, to be disconnected using the

DONE signal so that there is no bus contention when

the I/Os become active. In addition to controlling the

FPGA during start-up, other start-up techniques that

avoid contention include using isolation devices

between the FPGA and other circuits in the system,

reassigning I/O locations and maintaining I/Os as

3-stated outputs until contentions are resolved.

Each of these start-up options can be selected during

bit stream generation in

ORCA Foundry, using

Advanced Options. For more information, please see

the

ORCA Foundry documentation.

Reconfiguration

To reconfigure the FPGA when the device is operating

in the system, a low pulse is input into PRGM. The con-

figuration data in the FPGA is cleared, and the I/Os not

used for configuration are 3-stated. The FPGA then

samples the mode select inputs and begins reconfigu-

ration. When reconfiguration is complete, DONE is

released, allowing it to be pulled high.

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