OR2C04A datasheet(39/192 Pages) ETC

39 / 192 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 2 FPGAs

Clock Distribution Network (continued)

Alternatively, the clock can be routed from the spine to

the branches by using the BIDIs instead of the long-line

drivers. This results in added delay in the clock net, but

the clock skew is approximately equal to the clock

routed using the long-line drivers. This method can be

used to create a clock that is used in only one quad-

rant. The XH lines act as a clock spine, which is then

routed to perpendicular XH lines (the branches) using

the BIDIHs.

Clock signals, such as the output of a counter, can also

be generated in PLCs and routed onto an XL line,

which then acts as a clock spine. Although the clock

can be generated in any PLC, it is recommended that

the clock be located as close to the center of the FPGA

as possible to minimize clock skew.

Selecting Clock Input Pins

Any user I/O pin on an

ORCA FPGA can be used as a

very fast, low-skew clock input. Choosing the first clock

pin is completely arbitrary, but using a pin that is near

the center of an edge of the device (as shown in Fig-

ures 34 and 35) will provide the lowest skew clock net-

work. The pin-to-pin timing numbers in the Timing

Characteristics section of this data book assume that

the clock pin is in one of the four PICs at the center of

any side of the device.

Once the first clock pin has been chosen, there are

only two sets of pins (within the center four PICs on

each side of the device) that should not be chosen as

the second clock pin: a pin from the same PIC, and/or a

pin from the PIC on the exact opposite edge of the die

(i.e., if a pin from a PIC on the top edge is chosen for

the first clock, the same PIC on the bottom edge should

not be chosen for the second clock).

These rules should be followed iteratively until a total of

eight clocks (or other global signals) have been

selected: four from the left/right sides of the device, and

four from the top/bottom sides of the device. If more

than eight clocks are needed, then select another pin

outside the center four PICs to use primary-clock rout-

ing, use secondary clock routing for any pin, or use

local clock routing.

If it is desired to use a pin for one of the first eight

clocks that is not within the center four PICs of any side

of the device and primary clock routing is desired, the

pad names (see Pin Information) of the two clock pins

on the top or bottom of the device cannot be a multi-

plier of four PICs away. The same rule applies to clock

pins on the left or right side of the device.

The following equation can be used to determine pin

names:

Pad number = P[RL][TB]n ± (i x 4)[A – D]

Where i = 1—8, and n is the current PIC number.

For more information, please refer to

Utilizing the

ORCA®

OR2C/TxxA Clock Distribution Network Appli-

cation Note (AP97-055FPGA).

5-4481(F).r2

Figure 35. Secondary Clock Distribution

CLOCK

CLOCK SPINE

SEE DETAIL A

SEE DETAIL B

CLK PIN

BRANCHES

PFU

HCK

VCK

DETAIL B

DETAIL A

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