OR2C04A datasheet(43/192 Pages) ETC

43 / 192 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 2 FPGAs

FPGA States of Operation (continued)

5-2761(F).r4

Figure 38. Start-Up Waveforms

Partial Reconfiguration

All

ORCA device families have been designed to allow

a partial reconfiguration of the FPGA at any time. This

is done by setting a bit stream option in the previous

configuration sequence that tells the FPGA to not reset

all of the configuration RAM during a reconfiguration.

Then only the configuration frames that are to be modi-

fied need to be rewritten, thereby reducing the configu-

ration time.

Other bit stream options are also available that allow

one portion of the FPGA to remain in operation while a

partial reconfiguration is being done. If this is done, the

user must be careful to not cause contention between

the two configurations (the bit stream resident in the

FPGA and the partial reconfiguration bit stream) as the

second reconfiguration bit stream is being loaded.

Other Configuration Options

Configuration options used during device start-up were

previously discussed in the FPGA States of Operation

section of this data sheet. There are many other config-

uration options available to the user that can be set

during bit stream generation in

ORCA Foundry. These

include options to enable boundary scan, readback

options, and options to control and use the internal

oscillator after configuration.

Other useful options that affect the next configuration

(not the current configuration process) include options

to disable the global set/reset during configuration, dis-

able the 3-state of I/Os during configuration, and dis-

able the reset of internal RAMs during configuration to

allow for partial configurations (see above). For more

information on how to set these and other configuration

options, please see the

ORCA Foundry documenta-

tion.

Configuration Data Format

The

ORCA Foundry Development System interfaces

with front-end design entry tools and provides the tools

to produce a fully configured FPGA. This section dis-

cusses using the

ORCA Foundry Development System

to generate configuration RAM data and then provides

the details of the configuration frame format.

The

ORCA Series 2 series of FPGAs are enhanced

versions of the

ORCA ATT2Cxx/ATT2Txx architectures

that provide upward bit stream compatibility for both

series of devices as well as with each other.

DONE

ATT3000

I/O

GLOBAL

RESET

C1, C2, C3, OR C4

Di + 1

Di + 2

Di + 3

Di + 4

Di + 1

Di + 2

Di + 3

Di + 4

ORCA CCLK_SYNC

DONE IN

ORCA UCLK_NOSYNC

Di + 1

Di + 2

Di + 3

Di + 4

Di + 1

Di + 2

Di + 3

ORCA UCLK_SYNC

UCLK PERIOD

SYNCHRONIZATION UNCERTAINTY

DONE IN

U1, U2, U3, OR U4

DONE

I/O

GSRN

ACTIVE

DONE

I/O

GSRN

ACTIVE

DONE

I/O

GSRN

ACTIVE

DONE

I/O

GSRN

ACTIVE

UCLK

F = finished, no more CLKs required.

CCLK PERIOD

ORCA CCLK_NOSYNC

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