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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8945ECS/R датащи(PDF) 116 Page - Wolfson Microelectronics plc |
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WM8945ECS/R датащи(HTML) 116 Page - Wolfson Microelectronics plc |
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116 / 169 page  WM8945 Production Data w PD, May 2011, Rev 4.1 116 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 11 = 32 bits Note – see “Companding” for the selection of 8-bit mode. 1:0 FMT[1:0] 10 Digital Audio Interface Format 00 = Reserved 01 = Left Justified 10 = I2S format 11 = DSP/PCM mode Register 04h Audio Interface REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R5 (05h) Companding control 5 LOOPBACK 0 Digital Loopback Function 0 = No loopback 1 = Loopback enabled (ADC data output is directly input to DAC data input). 3 DAC_COMP 0 DAC Companding Enable 0 = Disabled 1 = Enabled 2 DAC_COMPM ODE 0 DAC Companding Mode 0 = µ-law 1 = A-law 1 ADC_COMP 0 ADC Companding Enable 0 = Disabled 1 = Enabled 0 ADC_COMPM ODE 0 ADC Companding Mode 0 = µ-law 1 = A-law Register 05h Companding control REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R6 (06h) Clock Gen control 15 OSC_CLK_EN A 0 Oscillator Enable 0 = Disabled 1 = Enabled This needs to be set when doing AUXADC measurements, or when a timeout clock is required for PGA zero cross or GPIO input detection 14:13 MCLK_PULL [1:0] 00 MCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 CLKOUT_SEL 0 CLKOUT Source Select 0 = SYSCLK 1 = FLL or MCLK (set by SYSCLK_SRC register) 11:10 CLKOUT_DIV [1:0] 00 CLKOUT Clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 9 SYSCLK_ENA 0 SYSCLK Enable |
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