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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8945ECS/R датащи(PDF) 115 Page - Wolfson Microelectronics plc |
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WM8945ECS/R датащи(HTML) 115 Page - Wolfson Microelectronics plc |
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115 / 169 page  Production Data WM8945 w PD, May 2011, Rev 4.1 115 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO DACR_ENA must be set to 1 when processing right channel data from the DAC or Digital Beep Generator. 0 DACL_ENA 0 Left DAC Enable 0 = Disabled 1 = Enabled DACR_ENA must be set to 1 when processing left channel data from the DAC or Digital Beep Generator. Register 03h Power management 2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R4 (04h) Audio Interface 15:14 DACDATA_PU LL[1:0] 00 DACDAT pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 13:12 FRAME_PULL [1:0] 00 LRCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 11:10 BCLK_PULL [1:0] 00 BCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 9 ADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = No data is output on right channel 8 ADCL_SRC 0 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = No data is output on left channel 6 DACL_SRC 0 Left DAC Data Source Select 0 = Left DAC outputs left interface data 1 = Left DAC outputs right interface data 5 BCLK_INV 0 BCLK Invert 0 = BCLK not inverted 1 = BCLK inverted 4 LRCLK_INV 0 LRCLK Polarity / DSP Mode A-B select. Right, left and I2S modes – LRCLK polarity 0 = Not Inverted 1 = Inverted DSP Mode – Mode A-B select 0 = MSB is available on 2 nd BCLK rising edge after LRCLK rising edge (mode A) 1 = MSB is available on 1 st BCLK rising edge after LRCLK rising edge (mode B) 3:2 WL[1:0] 10 Digital Audio Interface Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits |
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