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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8945ECS/R датащи(PDF) 74 Page - Wolfson Microelectronics plc |
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WM8945ECS/R датащи(HTML) 74 Page - Wolfson Microelectronics plc |
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74 / 169 page  WM8945 Production Data w PD, May 2011, Rev 4.1 74 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R6 (06h) Clock Gen control 15 OSC_CLK_ENA 0 Oscillator Enable 0 = Disabled 1 = Enabled This needs to be set when doing AUXADC measurements, or when a timeout clock is required for PGA zero cross or GPIO input detection 14:13 MCLK_PULL [1:0] 00 MCLK pull-up / pull-down Enable 00 = no pull-up or pull-down 01 = pull-down 10 = pull-up 11 = reserved 12 CLKOUT_SEL 0 CLKOUT Source Select 0 = SYSCLK 1 = FLL or MCLK (set by SYSCLK_SRC register) 11:10 CLKOUT_DIV [1:0] 00 CLKOUT Clock divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 9 SYSCLK_ENA 0 SYSCLK Enable 0 = Disabled 1 = Enabled 8 SYSCLK_SRC 0 SYSCLK Source Select 0 = MCLK 1 = FLL output 7:5 SYSCLK_DIV [2:0] 000 SYSCLK Clock divider (Sets the scaling for either the MCLK or FLL clock output, depending on SYSCLK_SRC) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 4 TOCLK_ENA 0 TOCLK Enabled (Enables timeout clock for GPIO level detection, AMU, and PGA zero cross timeout) 0 = Disabled 1 = Enabled R7 (07h) Additional control 3:0 SR [3:0] 1101 Audio Sample Rate select 0011 = 8kHz 0100 = 11.025kHz 0101 = 12kHz 0111 = 16kHz 1000 = 22.05kHz 1001 = 24kHz 1011 = 32kHz 1100 = 44.1kHz 1101 = 48kHz Table 49 Clocking and Sample Rate Control |
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