WM8945ECSSLASHR datasheet(98/169 Pages) WOLFSON

98 / 169 page

WM8945

Production Data

PD, May 2011, Rev 4.1

using the SPI_OD bit. If the open drain option is selected (SPI_OD = 1) then an external pull-up

resistor is required on the SDOUT or SDA output pin.

The Control Interface configuration bits are described in Table 66.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R20 (14h)

Control

Interface

SPI_OD

SDOUT pin configuration

(applies to 3-wire and 4-wire mode

only)

0 = SDOUT output is CMOS

1 = SDOUT output is open drain

SPI_4WIRE

SPI control mode select

0 = 3-wire using bidirectional SDA

1 = 4-wire using SDOUT

AUTO_INC

Enables address auto-increment

(applies to 2-wire / I2C mode only)

0 = Disabled

1 = Enabled

Table 66 Control Interface Configuration

2-WIRE (I2C) CONTROL MODE

In 2-wire mode, the WM8945 is a slave device on the control interface; SCLK is a clock input, while

SDA is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the

same interface, the WM8945 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An

external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by

the master.

In order to allow many devices to share a single 2-wire control bus, every device on the bus has a

unique 7-bit device ID (this is not the same as the 15-bit address of each register in the WM8945).

The WM8945 device ID is 34h. The LSB of the device ID is the Read/Write bit; this bit is set to logic 1

for “Read” and logic 0 for “Write”.

The WM8945 operates as a slave device only. The controller indicates the start of data transfer with a

high to low transition on SDA while SCLK remains high. This indicates that a device ID, register

address and data will follow. The WM8945 responds to the start condition and shifts in the next eight

bits on SDA (7-bit device ID + Read/Write bit, MSB first). If the device ID received matches the device

ID of the WM8945, then the WM8945 responds by pulling SDA low on the next clock pulse (ACK). If

the device ID is not recognised or the R/W bit is ‘1’ when operating in write only mode, the WM8945

returns to the idle condition and waits for a new start condition and valid address.

If the device ID matches the device ID of the WM8945, the data transfer continues as described

below. The controller indicates the end of data transfer with a low to high transition on SDA while

SCLK remains high. After receiving a complete address and data sequence the WM8945 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of

sequence at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns

to the idle condition.

The WM8945 supports the following read and write operations:



Single write



Single read



Multiple write using auto-increment



Multiple read using auto-increment

The sequence of signals associated with a single register write operation is illustrated in Figure 38.

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