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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8945ECS/R датащи(PDF) 43 Page - Wolfson Microelectronics plc |
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WM8945ECS/R датащи(HTML) 43 Page - Wolfson Microelectronics plc |
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43 / 169 page  Production Data WM8945 w PD, May 2011, Rev 4.1 43 To estimate the attack time for 10%-90%: Attack Time = Register Value * 2.24 For example, if DRC_ATK = 1.45ms/6dB, then the attack time for 10%-90% = 1.45ms * 2.24 = 3.25ms. The decay time for 10%-90% can be estimated using the graph in Figure 18. Figure 18 Decay Time for 10%-90% vs Register Value Decay Rate The decay rate register value read from the horizontal axis and the decay time for 10%-90% read from the vertical axis. For example, if DRC DRC_DCY = 743ms/6dB, then the estimate decay time for 10%-90% taken from the graph is 1.0s. ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically increasing the gain attack rate when required. The Anti-Clip feature is enabled using the DRC_ANTICLIP bit. Note that the feed-forward processing increases the latency in the input signal path. The DRC Anti- Clip control is described in Table 21. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R29 (1Dh) DRC Control 1 1 DRC_ANTICLIP 1 DRC Anti-clip Enable 0 = Disabled 1 = Enabled Table 21 DRC Anti-Clip Control |
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