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WM8945ECS/R датащи(PDF) 25 Page - Wolfson Microelectronics plc |
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WM8945ECS/R датащи(HTML) 25 Page - Wolfson Microelectronics plc |
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25 / 169 page ![]() Production Data WM8945 w PD, May 2011, Rev 4.1 25 MICROPHONE BIAS CONTROL The WM8945 provides a low noise reference voltage suitable for biasing electret condenser (ECM) type microphones via an external resistor. Refer to the “Applications Information” section for recommended components. The MICBIAS voltage is enabled using the MICB_ENA register bit; the voltage can be selected using the MICB_LVL bit, as described in Table 3. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R2 (02h) Power Management 1 4 MICB_ENA 0 Microphone Bias Enable 0 = Disabled 1 = Enabled R39 (27h) Input Ctrl 6 MICB_LVL 0 Microphone Bias Voltage control 0 = 0.9 x LDOVOUT 1 = 0.65 x LDOVOUT Table 3 Microphone Bias Control INPUT PGA GAIN CONTROL The volume control gain for the PGA is adjusted using the PGAL_VOL register field as described in Table 4. The gain range is -12dB to +35.25dB in 0.75dB steps. The gains on the inverting and non- inverting inputs to the PGA are always equal. The input PGA can be muted using the PGAL_MUTE mute bit. The PGA_VU bit controls the loading of digital volume control data. The PGAL_VOL control data is only loaded into the respective control register when PGA_VU = 1. To prevent “zipper noise”, a zero-cross function is provided on the input PGA. When this feature is enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long period without zero-crossings, a timeout function is provided. When the zero-cross function is enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The timeout clock is enabled using TOCLK_ENA. See “Clocking and Sample Rates” for the definition of this bit. Note that the zero-cross function can be supported without TOCLK enabled, but the timeout function will not be provided in this case. The Input PGA volume control register fields are described in Table 4. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R40 (28h) Left INP PGA gain ctrl 8 PGA_VU 0 Input PGA Volume Update Writing a 1 to this bit enables the Left PGA volume to be updated 7 PGAL_ZC 0 Left Input PGA Zero Cross Detector 0 = Change gain immediately 1 = Change gain on zero cross only 6 PGAL_MUTE 1 Left Input PGA Mute 0 = Disable Mute 1 = Enable Mute 5:0 PGAL_VOL [5:0] 01_0000 (0dB) Left Input PGA Volume 00_0000 = -12dB 00_0001 = -11.25dB … 01_0000 = 0dB ... 11_1111 = +35.25 (See Table 5 for volume range) Table 4 Input PGA Volume Control |
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