WM8945ECSSLASHR datasheet(44/169 Pages) WOLFSON

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WM8945

Production Data

PD, May 2011, Rev 4.1

Note that the Anti-Clip feature operates entirely in the digital domain. It cannot be used to prevent

signal clipping in the analogue domain nor in the source signal. Analogue clipping can only be

prevented by reducing the analogue signal gain or by adjusting the source signal.

The Anti-Clip and Quick Release features should not be used at the same time.

QUICK-RELEASE CONTROL

The DRC includes a Quick-Release feature to handle short transient peaks that are not related to the

intended source signal. For example, in handheld microphone recording, transient signal peaks

sometimes occur due to user handling, key presses or accidental tapping against the microphone.

The Quick Release feature ensures that these transients do not cause the intended signal to be

masked by the longer time constants of DRC_DCY.

The Quick-Release feature is enabled by setting the DRC_QR bit. When this bit is enabled, the DRC

measures the crest factor (peak to RMS ratio) of the input signal. A high crest factor is indicative of a

transient peak that may not be related to the intended source signal. If the crest factor exceeds the

level set by DRC_QR_THR, then the normal decay rate (DRC_DCY) is ignored and a faster decay

rate (DRC_QR_DCY) is used instead.

The DRC Quick-Release control bits are described in Table 22.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R29 (1Dh)

DRC Control 1

DRC_QR

DRC Quick-release Enable

0 = Disabled

1 = Enabled

R34 (22h)

DRC Control 6

3:2

DRC_QR_THR

[1:0]

DRC Quick-release threshold (crest

factor in dB)

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

1:0

DRC_QR_DCY

[1:0]

DRC Quick-release decay rate

(seconds/6dB)

00 = 0.725ms

01 = 1.45ms

10 = 5.8ms

11 = reserved

Table 22 DRC Quick-Release Control

The Anti-Clip and Quick Release features should not be used at the same time.

DRC INITIAL VALUE

The DRC can be set up to a defined initial condition based on the expected signal level when the

DRC is enabled. This can be set using the DRC_INIT bits in register R35 (23h) bits 4 to 0.

Note: This does NOT set the initial gain of the DRC. It sets the expected signal level of the DRC input

signal when the DRC is enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R35 (23h)

DRC Control 7

4:0

DRC_INIT

00000

Initial value at DRC startup

00000 = 0dB

00001 = -3.75dB

… (-3.75dB steps)

11111 = -116.25dB

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