HT95R34 datasheet(33/59 Pages) HOLTEK

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HT95R34

Rev. 1.10

February 18, 2009

Watchdog Timer

The Watchdog Timer is provided to prevent program

malfunctions or sequences from jumping to unknown lo-

cations, due to certain uncontrollable external events

such as electrical noise. It operates by providing a de-

vice reset when the WDT counter overflows. The WDT

clock is supplied by one of three sources selected by a

configuration option. These can be its own

self-contained dedicated internal WDT oscillator, exter-

nal 32768Hz or the instruction clock which is the system

clock divided by 4. Note that if the WDT configuration

option has been disabled, then any instruction relating

to its operation will result in no operation.

A configuration option can select the instruction clock,

which is the system clock divided by 4, as the WDT clock

source instead of the internal WDT oscillator. If the in-

struction clock is used as the clock source, it must be

noted that when the system enters the Power Down

Mode, as the system clock is stopped, then the WDT

clock source will also be stopped. Therefore the WDT

will lose its protecting purposes. In such cases the sys-

tem cannot be restarted by the WDT and can only be re-

started using external signals. For systems that operate

in noisy environments, using the internal WDT oscillator

or 32768Hz oscillator is therefore the recommended

choice.

Under Normal Mode and Green Mode operation, a WDT

time-out will initialise a device reset and set the status bit

TO. However, if the system is in the Sleep Mode or Idle

Mode, when a WDT time-out occurs, only the Program

Counter and Stack Pointer will be reset. Three methods

can be adopted to clear the contents of the WDT and the

WDT prescaler. The first is an external hardware reset,

which means a low level on the RES pin, the second is

using the watchdog software instructions and the third is

via a

²HALT² instruction.

There are two methods of using software instructions to

clear the Watchdog Timer, one of which must be chosen

by configuration option. The first option is to use the sin-

gle

²CLR WDT² instruction while the second is to use

the two commands

²CLR WDT1² and ²CLR WDT2². For

the first option, a simple execution of

²CLR WDT² will

clear the WDT while for the second option, both

²CLR

WDT1

² and ²CLR WDT2² must both be executed to

successfully clear the WDT. Note that for this second

option, if

²CLR WDT1² is used to clear the WDT, succes-

sive executions of this instruction will have no effect,

only the execution of a

²CLR WDT2² instruction will

clear the WDT. Similarly, after the

²CLR WDT2² instruc-

tion has been executed, only a successive

²CLR WDT1²

instruction can clear the Watchdog Timer.

W S 2

W D T S R e g i s t e r

b 7

b 0

W D T p r e s c a l e r r a t e s e l e c t

W S 2

W S 1

W S 0

W D T R a t e

1 : 1

1 : 2

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 2 8

N o t u s e d

W S 1 W S 0

Watchdog Timer Register

W D T C l o c k S o u r c e

C o n f i g u r a t i o n

O p t i o n

C l e a r W D T T y p e

C o n f i g u r a t i o n O p t i o n

C L R W D T 1 F l a g

C L R W D T 2 F l a g

C L R

9 - b i t C o u n t e r

W D T O s c i l l a t o r

f S Y S / 4

1 o r 2 I n s t r u c t i o n s

W D T C l o c k S o u r c e

f S

3 2 7 6 8 H z

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

Watchdog Timer

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