HT95R34 datasheet(16/59 Pages) HOLTEK

16 / 59 page

HT95R34

Rev. 1.10

February 18, 2009

· Z is set if the result of an arithmetic or logical operation

is zero; otherwise Z is cleared.

· OV is set if an operation results in a carry into the high-

est-order bit but not a carry out of the highest-order bit,

or vice versa; otherwise OV is cleared.

· PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by executing the

²HALT² instruction.

· TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set by a

WDT time-out.

In addition, on entering an interrupt sequence or execut-

ing a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status registers are important and if the subroutine

can corrupt the status register, precautions must be

taken to correctly save it.

Interrupt Control Register

- INTC0, INTC1

These two 8-bit register, known as the INTC0 and

INTC1 registers, control the operation of all interrupts.

By setting various bits within this register using standard

bit manipulation instructions, the enable/disable func-

tion of the external and timer interrupts can be inde-

pendently controlled. A master interrupt bit within this

and is used to set all of the interrupt enable bits on or off.

This bit is cleared when an interrupt routine is entered to

disable further interrupt and is set by executing the

²RETI² instruction.

Timer/Event Counter Registers

This device contains two 16-bit Timer/Event Counters,

which have associated register pairs known as TMR0L/

TMR0H and TMR1L/TMR1H. These are the locations

where the timers 16-bit value is located. Two associated

control registers, known as TMR0C and TMR1C, con-

tain the setup information for these two timers.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O

registers and their associated control registers play a

prominent role. All I/O ports have a designated register

correspondingly labeled as PA, PC, PD and PE. These

labeled I/O registers are mapped to specific addresses

within the Data Memory as shown in the Data Memory

table, which are used to transfer the appropriate output

or input data on that port. With each I/O port there is an

associated control register labeled PAC, PCC, PDC and

PEC, also mapped to specific addresses with the Data

Memory. Except PC2 and PC3, the control register

specifies which pins of that port are set as inputs and

which are set as outputs. PC2 or PC3 is NMOS output,

so the corresponding bit of the control register is not im-

plemented. To setup a pin as an input, the correspond-

ing bit of the control register must be set high, for an

output it must be set low. During program initialization, it

is important to first setup the control registers to specify

which pins are outputs and which are inputs before

reading data from or writing data to the I/O ports. One

flexible feature of these registers is the ability to directly

program single bits using the

²SET [m].i² and ²CLR

[m].i

² instructions. The ability to change I/O pins from

output to input and vice versa by manipulating specific

bits of the I/O control registers during normal program

operation is a useful feature of these devices.

DTMF Registers

- DTMFC, DTMFD, DTRXC, DTRXD

The device contains fully integrated DTMF receiver and

generator circuitry for decoding and generation of

DTMF signals. The DTMF receiver requires two regis-

ters to control its operation, a DTRXC control register to

control its overall function and a DTRXD register to store

the DTMF decoded signal data. The DTMF generator

also requires two registers for its operation, a DTMFC

store the digital codes that are to be generated as DMTF

signals.

Mode Register

- MODE

The device supports two system clock and four opera-

tion modes. The system clock could be 32768Hz or

3.58MHz and operation mode could be Normal, Green,

Sleep or Idle mode. These are all selected by the soft-

ware.

MFIC Register

- MFIC

PC0, PC5 and PC7 could be used to trigger an extra in-

terrupt. They are enabled or disabled individually by

bit0~bit2 of MFIC. When a multi-function interrupt oc-

curs, the programmer should check bit4~bit6 of MFIC to

determine the cause of the interrupt.

PFD Registers

- PFDC/PFDD

The device contains a Programmable Frequency Di-

vider function which can generate accurate frequencies

based on the system clock. The clock source, enable

function and output frequency is controlled using these

two registers.

RTCC Register

The device contains a Real Time Clock function other-

wise known as the RTC. To control this function a regis-

ter known as the RTCC register is provided which

provides the overall on/off control and time out flag.

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