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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT95R34 датащи(PDF) 29 Page - Holtek Semiconductor Inc |
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HT95R34 датащи(HTML) 29 Page - Holtek Semiconductor Inc |
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29 / 59 page  HT95R34 Rev. 1.10 29 February 18, 2009 Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 0 RES reset during power-on u u RES or LVR reset during normal operation 1 u WDT time-out reset during normal operation 1 1 WDT time-out reset during Power Down Note: ²u² stands for unchanged The following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counters The Timer Counters will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal regis- ters of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Register Reset (Power-on) RES or LVR Reset (Normal/Green) RES or LVR Reset (Sleep/Idle) WDT Time-out (Normal/Green) WDT Time-out (Sleep/Idle) IAR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu IAR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu BP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000H 0000H 0000H 0000H 0000H TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu STATUS - - 00 xxxx - - uu uuuu - - 01 uuuu - - 1u uuuu - - 11 uuuu INTC0 - 000 0000 - 000 0000 - 000 0000 - 000 0000 - uuu uuuu TMR0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 00 - 01 --- 00 - 01 --- 00 - 01 --- 00 - 01 --- uu - uu --- TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 00 - 01 --- 00 - 01 --- 00 - 01 --- 00 - 01 --- uu - uu --- PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 -- 11 1111 -- 11 1111 -- 11 1111 -- 11 uuuu -- uu PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu |
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