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HT95R34 датащи(PDF) 13 Page - Holtek Semiconductor Inc

номер детали HT95R34
подробное описание детали  I/O Type Phone 8-bit MCU with DTMF Receiver
PDF  59 Pages
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производитель  HOLTEK [Holtek Semiconductor Inc]
домашняя страница  http://www.holtek.com
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HT95R34 датащи(HTML) 13 Page - Holtek Semiconductor Inc

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HT95R34
Rev. 1.10
13
February 18, 2009
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user pro-
gram for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions, individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory. As the General Purpose Data Memory is
located within 11 different banks, it is first necessary to
ensure that the Bank Pointer is properly set to the cor-
rect value before accessing the General Purpose Data
Memory. Only Bank 0 data can be read directly. Indirect
Addressing of Bank 0 is executed using Indirect Ad-
dressing Register IAR0 and Memory Pointer MP0. Data
in Banks 1~10 can only be read indirectly using Indirect
Addressing Register IAR1 and Memory Pointer MP1.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writeable but some are protected and are readable only,
the details of which are located under the relevant Spe-
cial Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value
²00H². Although the Special Pur-
pose Data Memory registers are located in Bank 0, they
will still be accessible even if the Bank Pointer has se-
lected Banks 1~10.
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the RAM
Data Memory area. These registers ensure correct op-
eration of internal functions such as timers, interrupts,
watchdog, etc., as well as external functions such as I/O
data control. The location of these registers within the
RAM Data Memory begins at the address
²00H². Any
unused Data Memory locations between these special
function registers and the point where the General Pur-
pose Memory begins is reserved for future expansion
purposes, attempting to read data from these locations
will return a value of
²00H².
Indirect Addressing Register
- IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, al-
though having their locations in normal RAM register
space, do not actually physically exist as normal regis-
ters. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory ad-
dressing, where the actual memory address is speci-
fied. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corre-
sponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can ac-
cess data from both Bank 0 and Bank 1. As the Indirect
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
: U n u s e d b y t e , r e a d a s " 0 0 "
3 F H
3 0 H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
I A R 0
M P 0
I A R 1
M P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
I N T C 0
T M R 0 H
T M R 0 L
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P C
P C C
P D
P D C
P E
P E C
I N T C 1
D T M F C
D T M F D
D T R X C
D T R X D
R T C C
M O D E
2 B H
M F I C
P F D C
P F D D
2 C H
2 D H
2 E H
2 F H
Special Purpose Data Memory Structure



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