HT95R34 datasheet(26/59 Pages) HOLTEK

26 / 59 page

HT95R34

Rev. 1.10

February 18, 2009

A u t o m a t i c a l l y C l e a r e d b y I S R

- e x p e c t f o r P C 0 F , P C 5 F a n d P C 7 F

M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e

E x t e r n a l I n t e r r u p t

R e q u e s t F l a g E I F

T i m e r / E v e n t C o u n t e r 0

I n t e r r u p t R e q u e s t F l a g T 0 F

T i m e r / E v e n t C o u n t e r 1

I n t e r r u p t R e q u e s t F l a g T 1 F

E E I

E T 0 I

E T 1 I

E M I

A u t o m a t i c a l l y D i s a b l e d b y I S R

C a n b e E n a b l e d M a n u a l l y

P r i o r i t y

H i g h

I n t e r r u p t

P o l l i n g

P e r i p h e r a l I n t e r r u p t

R e q u e s t F l a g P E R F

E P E R I

R T C I n t e r r u p t

R e q u e s t F l a g R T C F

E R T C I

L o w

M u l t i - f u n c t i o n I n t e r r u p t

R e q u e s t F l a g M F F

E M F I

P C 0 I n t e r r u p t

R e q u e s t F l a g P C 0 F

E P C 0 I

P C 5 I n t e r r u p t

R e q u e s t F l a g P C 5 F

E P C 5 I

P C 7 I n t e r r u p t

R e q u e s t F l a g P C 7 F

E P C 7 I

Interrupt Structure

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests, the

following table shows the priority that is applied. These

can be masked by resetting the EMI bit.

Interrupt Source

All Devices Priority

Reset

External Interrupt

Timer 0 Interrupt

Timer 1 Interrupt

Peripheral Interrupt

Real Time Clock Interrupt

Multi-function Interrupt

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the INTC reg-

ister can prevent simultaneous occurrences.

External Interrupt

For an external interrupt to occur, the global interrupt en-

able bit, EMI, and external interrupt enable bit, EEI, must

first be set. An actual external interrupt will take place

when the external interrupt request flag, EIF, is set, a situ-

ation that will occur when a high to low transition appears

on the INT line. When the interrupt is enabled, the stack is

not full and a high to low transition appears on the exter-

nal interrupt pin, a subroutine call to the external interrupt

vector at location 04H, will take place. When the interrupt

is serviced, the external interrupt request flag, EIF, will be

automatically reset and the EMI bit will be automatically

cleared to disable other interrupts.

Timer/Event Counter Interrupt

For a Timer/Event Counter interrupt to occur, the global

interrupt enable bit, EMI, and the corresponding timer

interrupt enable bit, ET0I or ET1I, must first be set. An

actual Timer/Event Counter interrupt will take place

when the Timer/Event Counter request flag, T0F or T1F,

is set, a situation that will occur when the Timer/Event

Counter overflows. When the interrupt is enabled, the

stack is not full and a Timer/Event Counter overflow oc-

curs, a subroutine call to the timer interrupt vector at lo-

cation 08H or 0CH, will take place. When the interrupt is

serviced, the timer interrupt request flag, T0F or T1F, will

be automatically reset and the EMI bit will be automati-

cally cleared to disable other interrupts.

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