SC16IS752IPW datasheet(13/59 Pages) NXP

13 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

13 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.4 Hardware Reset, Power-On Reset (POR) and Software Reset

These three reset methods are identical and will reset the internal registers as indicated in

Table 4.

Table 4 summarizes the state of register after reset.

Remark: Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the

top-level reset signal RESET, POR and Software Reset, that is, they hold their

initialization values during reset.

Table 5 summarizes the state of output signals after reset.

Table 4.

Reset state

Interrupt Enable Register

all bits cleared

Interrupt Identiﬁcation Register

bit 0 is set; all other bits cleared

FIFO Control Register

all bits cleared

Line Control Register

reset to 0001 1101 (0x1D)

Modem Control Register

all bits cleared

Line Status Register

bit 5 and bit 6 set; all other bits cleared

Modem Status Register

bits 3:0 cleared; bits 7:4 input signals

Enhanced Features Register

all bits cleared

Receive Holding Register

pointer logic cleared

Transmit Holding Register

pointer logic cleared

Transmission Control Register

all bits cleared

Trigger Level Register

all bits cleared

Transmit FIFO level

reset to 0100 0000 (0x40)

Receive FIFO level

all bits cleared

I/O direction

all bits cleared

I/O interrupt enable

all bits cleared

I/O control

all bits cleared

Extra Features Control Register

all bits cleared

Table 5.

Output signals after reset

Signal

Reset state

HIGH

RTS

HIGH

I/Os

inputs

IRQ

HIGH by external pull-up

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