SC16IS752IPW datasheet(31/59 Pages) NXP

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SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

31 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.17 I/O Interrupt Enable register (IOIntEna)

This register enables the interrupt due to a change in the I/O conﬁgured as inputs. If

GPIO[7:4] or GPIO[3:0] are programmed as modem pins, their interrupt generation must

be enabled via IER[3]. In this case, IOIntEna will have no effect on GPIO[7:4] or

GPIO[3:0].

8.18 I/O Control register (IOControl)

Remark: As I/O pins, the direction, state, and interrupt enable of GPIO are controlled by

the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI, DSR

pins will not be reﬂected in MSR[7:5] or MSR[3:1], and any change of state on these three

pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the state of

the DTR pin cannot be controlled by MCR[0].

As modem CD, RI, DSR pins, the status at the input of these three pins can be read from

MSR[7:5] and MSR[3:1], and the state of the DTR pin can be controlled by MCR[0]. Also,

if modem status interrupt bit is enabled, IER[3], a change of state on RI, CD, DSR pins will

trigger a modem interrupt. The IODir, IOState, and IOIntEna registers will not have any

effect on these three pins.

Table 28.

IOIntEna register bits description

Bit

Symbol

Description

7:0

IOIntEna

Input interrupt enable.

0 = a change in the input pin will not generate an interrupt

1 = a change in the input will generate an interrupt

Table 29.

IOControl register bits description

Bit

Symbol

Description

7:4

reserved

These bits are reserved for future use.

SRESET

Software Reset. A write to this bit will reset the device. Once the

device is reset this bit is automatically set to logic 0.

GPIO[3:0] or

RIB, CDB,

DTRB, DSRB

This bit programs GPIO[3:0] as I/O pins or as modem pins.

0 = I/O pins

1 = GPIO[3:0] emulate RIB, CDB, DTRB, DSRB

GPIO[7:4] or

RIA, CDA,

DTRA, DSRA

This bit programs GPIO[7:4] as I/O pins or as modem pins.

0 = I/O pins

1 = GPIO[7:4] emulate RIA, CDA, DTRA, DSRA

IOLATCH

Enable/disable inputs latching.

0 = input value are not latched. A change in any input generates an

interrupt. A read of the input register clears the interrupt. If the input

goes back to its initial logic state before the input register is read,

then the interrupt is cleared.

1 = input values are latched. A change in the input generates an

interrupt and the input logic value is loaded in the bit of the

corresponding input state register (IOState). A read of the IOState

logic state before the interrupt register is read, then the interrupt is

not cleared and the corresponding bit of the IOState register keeps

the logic value that initiates the interrupt.

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