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SC16IS752IPW датащи(PDF) 41 Page - NXP Semiconductors

номер детали SC16IS752IPW
подробное описание детали  Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
PDF  59 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC16IS752IPW датащи(HTML) 41 Page - NXP Semiconductors

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R/W = 0; A[3:0] = register address; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B
a. Register write
R/W = 1; A[3:0] = register address; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B
b. Register read
R/W = 0; A[3:0] = 0000; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B
c. FIFO write cycle
R/W = 1; A[3:0] = 0000; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B
d. FIFO read cycle
(1) Last bit (D0) of the last byte to be written to the transmit FIFO.
(2) Last bit (D0) of the last byte to be read from the receive FIFO.
Fig 20. SPI operation
SI
A1
A2
A3
R/W
SCLK
CH1
A0
X
CH0
D6
D7
D4
D5
D2
D3
D0
D1
002aab433
SI
A1
A2
A3
R/W
SCLK
CH1
A0
X
CH0
002aab434
SO
D6
D7
D4
D5
D2
D3
D0
D1
SI
A1
A2
A3
R/W
SCLK
CH1
A0
X
CH0
D6
D7
D4
D5
D2
D3
D0
D1
002aab435
D6
D7
D4
D5
D2
D3
D0
D1
last bit(1)
SI
A1
A2
A3
R/W
SCLK
CH1
A0
X
CH0
002aab436
SO
D6
D7
D4
D5
D2
D3
D0
D1
D0
D1
last bit(2)
D6
D7
D4
D5
D2
D3



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