SC16IS752IPW datasheet(6/59 Pages) NXP

6 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

6 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

6.2 Pin description

Table 2.

Pin description

Symbol

Type

Description

TSSOP28

HVQFN32

CS/A0

SPI chip select or I2C-bus device address select A0. If SPI conﬁguration

is selected by I2C/SPI pin, this pin is the SPI chip select pin

(Schmitt-trigger active LOW). If I2C-bus conﬁguration is selected by

I2C/SPI pin, this pin along with A1 pin allows user to change the device’s

base address.

To select the device address, please refer to Table 32.

CTSA

UART clear to send (active LOW), channel A. A logic 0 (LOW) on the

CTSA pin indicates the modem or data set is ready to accept transmit

data from the SC16IS752/SC16IS762. Status can be tested by reading

MSR[4]. This pin only affects the transmit and receive operations when

Auto-CTS function is enabled via the Enhanced Features Register

EFR[7] for hardware ﬂow control operation.

CTSB

UART clear to send (active LOW), channel B. A logic 0 on the CTSB pin

indicates the modem or data set is ready to accept transmit data from the

SC16IS752/SC16IS762. Status can be tested by reading MSR[4]. This

pin only affects the transmit and receive operations when Auto-CTS

function is enabled via the Enhanced Features Register EFR[7] for

hardware ﬂow control operation.

I2C/SPI

I2C-bus or SPI interface select. I2C-bus interface is selected if this pin is

at logic HIGH. SPI interface is selected if this pin is at logic LOW.

IRQ

Interrupt (open-drain, active LOW). Interrupt is enabled when interrupt

sources are enabled in the Interrupt Enable Register (IER). Interrupt

conditions include: change of state of the input pins, receiver errors,

available receiver buffer data, available transmit buffer space, or when a

modem status ﬂag is detected. An external resistor (1 k

Ω for 3.3 V,

1.5 k

Ω for 2.5 V) must be connected between this pin and V

DD.

SI/A1

SPI data input pin or I2C-bus device address select A1. If SPI

conﬁguration is selected by I2C/SPI pin, this is the SPI data input pin. If

I2C-bus conﬁguration is selected by I2C/SPI pin, this pin along with the

A0 pin allows user to change the slave base address. To select the

device address, please refer to Table 32.

SPI data output pin. If SPI conﬁguration is selected by I2C/SPI pin, this is

a 3-stateable output pin. If I2C-bus conﬁguration is selected by the

I2C/SPI pin, this pin is undeﬁned and must be left as not connected.

SCL/SCLK

I2C-bus or SPI input clock.

SDA

I/O

I2C-bus data input/output, open-drain if I2C-bus conﬁguration is selected

by I2C/SPI pin. If SPI conﬁguration is selected, this is not used and must

be connected to VSS.

GPIO0/DSRB

I/O

Programmable I/O pin or modem DSRB[1]

GPIO1/DTRB

I/O

Programmable I/O pin or modem DTRB[1]

GPIO2/CDB

I/O

Programmable I/O pin or modem CDB[1]

GPIO3/RIB

I/O

Programmable I/O pin or modem RIB[1]

GPIO4/DSRA

I/O

Programmable I/O pin or modem DSRA[2]

GPIO5/DTRA

I/O

Programmable I/O pin or modem DTRA[2]

GPIO6/CDA

I/O

Programmable I/O pin or modem CDA[2]

GPIO7/RIA

I/O

Programmable I/O pin or modem RIA[2]

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