SC16IS752IPW datasheet(37/59 Pages) NXP

37 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

37 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

10.2 Addressing and transfer formats

Each device on the bus has its own unique address. Before any data is transmitted on the

bus, the master transmits on the bus the address of the slave to be accessed for this

transaction. A well-behaved slave with a matching address, if it exists on the network,

should of course acknowledge the master's addressing. The addressing is done by the

ﬁrst byte transmitted by the master after the START condition.

An address on the network is seven bits long, appearing as the most signiﬁcant bits of the

address byte. The last bit is a direction (R/W) bit. A zero indicates that the master is

transmitting (‘write’) and a one indicates that the master requests data (‘read’). A complete

data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is

shown in Figure 16.

When an address is sent, each device in the system compares the ﬁrst seven bits after the

START with its own address. If there is a match, the device will consider itself addressed

by the master, and will send an acknowledge. The device could also determine if in this

transaction it is assigned the role of a slave receiver or slave transmitter, depending on the

R/W bit.

Each node of the I2C-bus network has a unique seven-bit address. The address of a

microcontroller is of course fully programmable, while peripheral devices usually have

ﬁxed and programmable address portions.

When the master is communicating with one device only, data transfers follow the format

of Figure 16, where the R/W bit could indicate either direction. After completing the

transfer and issuing a STOP condition, if a master would like to address some other

device on the network, it could start another transaction by issuing a new START.

Another way for a master to communicate with several different devices would be by using

a ‘Repeated START’. After the last byte of the transaction was transferred, including its

acknowledge (or negative acknowledge), the master issues another START, followed by

address byte and data without effecting a STOP. The master may communicate with a

number of different devices, combining ‘reads’ and ‘writes’. After the last transfer takes

place, the master issues a STOP and releases the bus. Possible data formats are

demonstrated in Figure 17. Note that the repeated START allows for both change of a

slave and a change of direction, without releasing the bus. We shall see later on that the

change of direction feature can come in handy even when dealing with a single device.

Fig 16. A complete data transfer

SDA

SCL

0 to 6

ACK

002aab046

START

condition

STOP

condition

address

R/W

0 to 6

data

ACK

0 to 6

data

ACK

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