SC16IS752IPW datasheet(32/59 Pages) NXP

32 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

32 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.19 Extra Features Control Register (EFCR)

[1]

For SC16IS762 only.

8.20 Division registers (DLL, DLH)

These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock

in the baud rate generator. DLH stores the most signiﬁcant part of the divisor. DLL stores

the least signiﬁcant part of the divisor.

Note that DLL and DLH can only be written to before Sleep mode is enabled (before

IER[4] is set).

Table 30.

Extra Features Control Register bits description

Bit

Symbol

Description

IRDA MODE

IrDA mode.

0 = IrDA SIR, 3

⁄

16 pulse ratio, data rate up to 115.2 kbit/s

1 = IrDA SIR, 1

⁄

4 pulse ratio, data rate up to 1.152 Mbit/s

[1]

reserved

RTSINVER

Invert RTS signal in RS-485 mode.

0: RTS = 0 during transmission and RTS = 1 during reception

1: RTS = 1 during transmission and RTS = 0 during reception

RTSCON

Enable the transmitter to control the RTS pin.

0: transmitter does not control RTS pin

1: transmitter controls RTS pin

reserved

TXDISABLE

Disable transmitter. UART does not send serial data out on the

transmit pin, but the transmit FIFO will continue to receive data from

host until full. Any data in the TSR will be sent out before the

transmitter goes into disable state.

0: transmitter is enabled

1: transmitter is disabled

RXDISABLE

Disable receiver. UART will stop receiving data immediately once this

bit is set to 1, and any data in the TSR will be sent to the receive FIFO.

User is advised not to set this bit during receiving.

0: receiver is enabled

1: receiver is disabled

9-BIT MODE

Enable 9-bit or Multidrop mode (RS-485).

0: normal RS-232 mode

1: enables RS-485 mode

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