SC16IS752IPW datasheet(11/59 Pages) NXP

11 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

11 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

There are two other enhanced features relating to software ﬂow control:

• Xon Any function (MCR[5]): Receiving any character will resume operation after

recognizing the Xoff character. It is possible that an Xon1 character is recognized as

an Xon Any character, which could cause an Xon2 character to be written to the

RX FIFO.

• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the

special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The

Xoff interrupt is cleared by a read of the Interrupt Identiﬁcation Register (IIR). The

special character is transferred to the RX FIFO.

7.3.1 Receive ﬂow control

When software ﬂow control operation is enabled, the SC16IS752/SC16IS762 will

compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1

and Xoff2 must be received sequentially). When the correct Xoff characters are received,

transmission is halted after completing transmission of the current character. Xoff

detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go LOW.

To resume transmission, an Xon1/Xon2 character must be received (in certain cases

Xon1 and Xon2 must be received sequentially). When the correct Xon characters are

received, IIR[4] is cleared, and the Xoff interrupt disappears.

7.3.2 Transmit ﬂow control

Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the halt trigger level

programmed in TCR[3:0], or the selectable trigger level in FCR[7:6].

Xon1/Xon2 character is transmitted when the RX FIFO reaches the resume trigger level

programmed in TCR[7:4], or falls below the lower selectable trigger level in FCR[7:6].

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an

ordinary character from the FIFO. This means that even if the word length is set to be 5, 6,

or 7 bits, then the 5, 6, or 7 least signiﬁcant bits of Xoff1/Xoff2, Xon1/Xon2 will be

transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but

this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software ﬂow control and hardware ﬂow control will never be enabled

simultaneously. Figure 7 shows an example of software ﬂow control.

SC16IS752IPW датащи(PDF) 11 Page - NXP Semiconductors