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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC16IS752IPW датащи(PDF) 40 Page - NXP Semiconductors |
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SC16IS752IPW датащи(HTML) 40 Page - NXP Semiconductors |
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40 / 59 page  SC16IS752_SC16IS762_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 19 May 2008 40 of 59 NXP Semiconductors SC16IS752/SC16IS762 Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR The register read cycle (see Figure 19) commences in a similar manner, with the master sending a slave address with the direction bit set to WRITE with a following subaddress. Then, in order to reverse the direction of the transfer, the master issues a Repeated START followed again by the device address, but this time with the direction bit set to READ. The data bytes starting at the internal subaddress will be clocked out of the device, each followed by a master-generated acknowledge. The last byte of the read cycle will be followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated by a STOP signal. White block: host to SC16IS752/SC16IS762 Grey block: SC16IS752/SC16IS762 to host (1) See Table 33 for additional information. Fig 18. Master writes to slave S SLAVE ADDRESS 002aab047 W A REGISTER ADDRESS(1) A nDATA A P White block: host to SC16IS752/SC16IS762 Grey block: SC16IS752/SC16IS762 to host (1) See Table 33 for additional information. Fig 19. Master read from slave S SLAVE ADDRESS 002aab048 W A REGISTER ADDRESS(1) A NA P S SLAVE ADDRESS R A nDATA A LAST DATA Table 33. Register address byte (I2C) Bit Name Function 7 - not used 6:3 A[3:0] UART’s internal register select 2:1 CH1, CH0 Channel select. 00 = channel A 01 = channel B 10 = reserved 11 = reserved 0 - not used |
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