SC9RS08KA2 datasheet(103/134 Pages) FREESCALE

103 / 134 page

Chapter 12 Development Support

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

103

•

Subsequent bits must occur within 512 BDC cycles of the last bit sent.

12.4

BDC Registers and Control Bits

The BDC contains two non-CPU accessible registers:

•

The BDC status and control register (BDCSCR) is an 8-bit register containing control and status

bits for the background debug controller.

•

The BDC breakpoint register (BDCBKPT) holds a 16-bit breakpoint match address.

These registers are accessed with dedicated serial BDC commands and are not located in the memory

space of the target MCU (so they do not have addresses and cannot be accessed by user programs).

Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written

at any time. For example, the ENBDM control bit may not be written while the MCU is in active

background mode. This prevents the ambiguous condition of the control bit forbidding active background

mode while the MCU is already in active background mode. Also, the status bits (BDMACT, WS, and

WSF) are read-only status indicators and can never be written by the WRITE_CONTROL serial BDC

command.

12.4.1

BDC Status and Control Register (BDCSCR)

This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)

but is not accessible to user programs because it is not located in the normal memory map of the MCU.

543

210

ENBDM

BDMACT

BKPTEN

FTS

0WS

WSF

Normal

Reset

000

Reset in

Active BDM:

110

000

= Unimplemented or Reserved

Figure 12-6. BDC Status and Control Register (BDCSCR)

Table 12-1. BDCSCR Register Field Descriptions

Field

Description

ENBDM

Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly

after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal

reset clears it

. If the application can go into stop mode, this bit is required to be set if debugging capabilities are

required

0 BDM cannot be made active (non-intrusive commands still allowed).

1 BDM can be made active to allow active background mode commands.

BDMACT

Background Mode Active Status — This is a read-only status bit

0 BDM not active (user application program running).

1 BDM active and waiting for serial commands.

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